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Acqiris SA230E, User Manual

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Acqiris SA230E User Manual Download Page 59

Control and Synchronization

Acqiris SA230E User's Manual

59

Chapter 5

Control and Synchronization

5.1 External reference

60

5.2 Trigger modes and time-stamps

60

5.3 Trigger output

65

5.4 Multi-purpose inputs and outputs

67

Summary of Contents for SA230E

Page 1: ...Acqiris SA230E Acquisition Module 1 channel 14 bit 4 GS s DC up to 2 GHz bandwidth User s Manual...

Page 2: ...r agreement and written consent from Acqiris SA as governed by international copyright laws Version August 2019 Contact us Acqiris Americas contact americas acqiris com Acqiris Europe contact emea acq...

Page 3: ...urable options 7 Main Module Features 8 1 1 SA230E front panel features 9 1 2 Channel input specifications 10 1 3 Sampling and data acquisition 12 1 4 Trigger 13 1 5 Calibration 15 Signal Acquisition...

Page 4: ...rate a software trigger 81 7 5 How to enable or bypass the bandwidth limiter 82 7 6 How to set the external trigger 83 7 7 How to perform binary decimation depending on firmware 84 7 8 How to load a n...

Page 5: ...lent signal fidelity across a wide bandwidth This new card and module generation with advanced real time processing capabilities is designed for embedded OEM applications in a variety of challenging m...

Page 6: ...ge SFDR and signal noise ratio SNR performances in high frequencies it is ideal for OEM applications requiring digitizer sampling at wide bandwidth and very high dynamic range especially at 500 mV ful...

Page 7: ...GB MEA option 8 GB MEB option ADC Card modes Digitizer mode DGT Real time averaging AVG option Real time peak listing PKL option Optional features Simultaneous acquisition and readout Streaming recor...

Page 8: ...Features 8 Acqiris SA230E User s Manual Chapter 1 Main Module Features 1 1 SA230E front panel features 9 1 2 Channel input specifications 10 1 3 Sampling and data acquisition 12 1 4 Trigger 13 1 5 Cal...

Page 9: ...signal programmable 50 source LVCMOS3 3V I O 1 2 3 MMCX User configurabledigitalInput Outputsignal DC coupling LVCMOS3 3V Output 50 source Input 5Vmax REF IN MMCX Externalreferenceclockinput AC couple...

Page 10: ...voltage page 77 Impedance coupling The input channel termination is 50 The input coupling is DC Input protection The input amplifiers are designed to accept signals within the absolute maximum operati...

Page 11: ...MHz 200 MHz or 700 MHz Also see Programing section How to enable or bypass the bandwidth limiter page 82 Vertical resolution The SA230E uses 14 bit ADCs giving 16384 levels at each input full scale r...

Page 12: ...sition Modes SA230E 4GS s 1 14bits Singleor multi record upto131 072 or continuoussteamingwithCST option Table 1 3 Acquisition sampling rate and resolution per channel Data acquisition modes and funct...

Page 13: ...edance with DC coupling Trigger input bandwidths The bandwidth depends on the trigger source Channel trigger The 3 dB bandwidth of the comparator of the channel triggers is from DC to 2 GHz External t...

Page 14: ...it passes through the specified trigger level Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage Negative slope indicates the signal is transitioning fr...

Page 15: ...e can be time consuming because of the many possible configuration states Therefore the self calibration is performed only for the current configuration state and is mandatory before making the first...

Page 16: ...nding to all datasheet specifications for every installed option If needed the DUT is adjusted and re qualified ensuring it is in line with full specifications Our ADC modules are calibrated at factor...

Page 17: ...and eventually for each of your system This section details the acquisition modes 2 1 Digitizer acquisition mode 18 2 2 Real time averaging mode AVG option 22 2 3 Real time peak listing mode PKL opti...

Page 18: ...same time to within a small fraction of the maximum sampling rate The single record acquisition mode is the normal operation of most ADC module products In this mode an acquisition consists of a wavef...

Page 19: ...s for Single record or multi records acquisitions are available For IVI C C1 Program Files IVI Foundation IVI Drivers AqMD3 Examples IVI C For IVI NET C Program Files IVI Foundation IVI Drivers AqMD3...

Page 20: ...d Acquisition memory Max sampling rate Max recording time window at higher sampling rate SA230P MEA default 4GB 4GS s 500ms MEB optional 8GB 1s Table 2 2 Maximum recorded time at maximum sampling rate...

Page 21: ...hould be considered when using the samples values in ADC code format Using basic digitizer function without DGT option If the ADC module had been ordered with a specific application mode and without t...

Page 22: ...h is provided in output The main features are Averaging from 1 up to 65k in steps of 1 trigger Effective acquisition length up to 1M Samples Noise suppressed accumulation NSA Self Trigger mode for min...

Page 23: ...inly on the PCIe connection and PC multitasking activity The time to initiate the next acquisition The function simultaneous acquisition and readout CST can be combined with the averager mode removing...

Page 24: ...from data values which are higher than the configured threshold This parameter is defined as signed left aligned 16 bit ADC code and in the range of Threshold 32767 Threshold if Threshold 0 Threshold...

Page 25: ...rument Acquisition Mode AcquisitionMode Averager IVI C The attribute AQMD3_ATTR_ACQUISITION_MODE ViInt32 must be set to value AQMD3_VAL_ ACQUISITION_MODE_AVERAGER AqMD3_SetAttributeViInt32 session AQM...

Page 26: ...ion in Averager or Peak Detection mode Returned waveform data units are Volts Attributes Attribute Description AQMD3_ATTR_ ACQUISITION_MODE The acquisition mode i e Averager AQMD3_ATTR_ ACQUISITION_NU...

Page 27: ...se is subtractedfrom datavalues whichare higherthantheconfiguredthreshold The units areADC counts Threshold Specifies thethresholdof theNoiseSup pressedAccumulation Eachdatavalue must exceedthethresho...

Page 28: ...ime providing in output only the characteristics of the relevant waveform peaks In case of input saturation the number of sample in overrange is provided Description Principe The peak list mode is bas...

Page 29: ...ximum order is fixed by the firmware Pulse Detection A pulse is detected when the signal samples go through the following states 1 Rising edge The sample values exceed a configurable data threshold an...

Page 30: ...litude are determined using an interpolation The interpolation is based on a 2nd degree polynomial and applied to 3 points around the maximum found by the peak detection algorithm Computed Pulse Chara...

Page 31: ...lter that applies to sample values Range strict positive Maximum value is determined by firmware Minimum value is 1 and corresponds to disabling smoothing PulseDerivativeHysteresis Pulse derivative hy...

Page 32: ...on user requirement In normal operation this mode shall be disabled If enabled the Data storage mode uses much of the available output data bandwidth Therefore in this mode some pulse descriptors mig...

Page 33: ...be stored in order and pulse descriptors from the previous record might be stored after the trigger descriptor of the subsequent record The record counter must be used to assign pulse descriptors to...

Page 34: ...rs 203 184 20 PeakY Signedfixedpoint 3frac tionalbits PeakYcoordinate 231 208 24 Center ofMassX unsignedfixedpoint 8 fractionalbits fixedpoint 8fractionalbits Center ofMassXcoordinaterelativetothe fir...

Page 35: ...e API IAqMD3Acquisition Mode PeakListacquisitioncanbeselectedbysettingthe attributetothefollowingmode AcquisitionMode PeakList IAqMD3ChannelPeakList DataStorageMode Canbesetwithoneofthefollowingvalues...

Page 36: ...IST_DATA_STORAGE_ MODE_FILTERED_DERIVATIVE AQMD3_ATTR_CHANNEL_PEAK_LIST_BASELINE AQMD3_ATTR_CHANNEL_PEAK_LIST_VALUE_ SMOOTHING_LENGTH AQMD3_ATTR_CHANNEL_PEAK_LIST_DERIVATIVE_ SMOOTHING_LENGTH AQMD3_AT...

Page 37: ...and readout modes are Single record mode one shot with single waveform with a single trigger Multi record mode one shot with multiple waveforms with multiple triggers Figure 3 1 Acquisition sequence...

Page 38: ...is section focuses on the usage of simultaneous acquisition and readout in digitizer mode The next section presents the Averager with simultaneous acquisition and readout AVG CST page 47 In a standard...

Page 39: ...to the PCIe interface The size of the pipe represents the volume of data flow that can be extracted from the module When the stream data rate is larger of the available PCIe data bandwidth an overflo...

Page 40: ...urrent call This number is always numElementsToFetch firstValidElement represents the first valid Int32 element in the returned data buffer It is used for data alignment reasons elements contains the...

Page 41: ...that can be sustained without overflow is limited by the PCIe sustained throughput on the target system i e it depends on trigger rate and host computer and operating system settings With optimized se...

Page 42: ...brSampleElementsToFetch 2 data alignment data unwrapping overheads only in single channel mode or vector ViInt32 sampleElements nbrSampleElementsToFetch alignmentOverhead data alignment overhead only...

Page 43: ...ing mode an Abort should be performed The different streams are implemented as instances of stream Repeated capabilities There are several types of stream Repeated capabilities Detailed help may be fo...

Page 44: ...ivenindex FetchDataInt32 This functionreturns astream of Elements TheEle mentSizeInBits andthemeaningof eachElement depend ontheStreamType Enabled Specifies whetherthestream is enabledonthemodule Type...

Page 45: ...230E User s Manual 45 IVI C Function AqMD3_StreamFetchDataInt32 This functionreturns astream of Elements TheEle mentSizeInBits andthemeaningof eachElement dependonthe StreamType AqMD3_GetStreamName Re...

Page 46: ...edonthemodule AQMD3_ATTR_STREAM_TYPE Indicatesthetypeofthestream AQMD3_ATTR_STREAM_GRANULARITY_IN_ BYTES Indicatesthegranularityofdatafor theFetchDataoper ations AQMD3_ATTR_STREAM_MAX_SIZE_IN_BYTES In...

Page 47: ...de AVG option page 22 The addition of simultaneous acquisition and readout feature CST on top of real time averaging enables minimal dead time between accumulations Functional description The architec...

Page 48: ...tained without losing any trigger The number of averages for an accumulation sequence can be selected from 1 up to 65k triggers When the abort command occurs the ongoing partial accumulated record can...

Page 49: ...CST Acqiris SA230E User s Manual 49 Figure 3 7 AVG CST acquisition sequence Performance Excepted for small number of averages the architecture enables no trigger loss The maximum performance of the sy...

Page 50: ...rocessing features that can be enable e g to optimize signal performance or reduce data volume depending on each application These features are common to the acquisition modes excepted when specified...

Page 51: ...stabilization Figure 4 1 Continuous baseline stabilization example Principle The baseline correction is not enabled by default When activated the baseline stabilization algorithm consists in the main...

Page 52: ...s a way to exclude unwanted signal values from the baseline calculation assuming that there is no or very low active signal outside the acquisition window Configuration For more information to configu...

Page 53: ...y for baseline correction AQMD3_ATTR_CHANNEL_ BASELINE_CORRECTION_ PULSE_THRESHOLD Baseline pulse detection threshold as signed left aligned 16 bit ADC code IVI NET Interface Method Property name Desc...

Page 54: ...sampling rate Decimation and bandwidth limitation The table below provides the behavior when combining decimation and bandwidth limitation Decimation factor Effective sampling rate Bandwidth typ ical...

Page 55: ...sion is applied the NSA settings or the signal thresholding Configuration IVI C Attribute Description AQMD3_ATTR_CHANNEL_ DATA_INVERSION_ ENABLED Specifies whether the data acquired is inverted IVI NE...

Page 56: ...com By default Custom Equalization is equivalent to Equalization Off The equalization option is supported for both digitizer DGT and averager AVG modes Driver property attribute The equalization mode...

Page 57: ...ency response superior to 0 dB for high frequencies see above the Bode plot without equalization there is a risk of signal overrange at the ADC output even if the input signal is included within the A...

Page 58: ...amplesareoutsideofthenumericrange oftheADC output Defaultistrue IVI NET IAqMD3Acquisition ErrorOnOverrangeEnabled Driver Error Description IVI C AQMD3_ERROR_ADC_OVERRANGE ADC isinoverrangeacquisitiond...

Page 59: ...Synchronization Acqiris SA230E User s Manual 59 Chapter 5 Control and Synchronization 5 1 External reference 60 5 2 Trigger modes and time stamps 60 5 3 Trigger output 65 5 4 Multi purpose inputs and...

Page 60: ...the specified value you must remember to compensate for the difference in your application since the ADC module and the driver have no way to know about such deviations Parameter Value Tolerance Nomin...

Page 61: ...eatures baseline stabilization zero suppress ZS1 data inversion capability or simultaneous acquisition and readout CST Figure 5 1 Acquisition timeline depending on the trigger delay defined Trigger de...

Page 62: ...larity is less than one sample interval 0s Averager acquisition mode In this mode the pre trigger delay is not supported Thus the minimum trigger delay is 0s The maximum trigger delay is given by 224...

Page 63: ...asure is zero or the waveform is empty EndTime EndTime is the time between the last valid data point in the waveform and the TriggerTime Positive values of EndTime indicate that it occurred after the...

Page 64: ...ny specific demand relative to this limitation or to self trigger Parameters ActiveSource IAqMD3Trigger ActiveSource property Specifies the trigger source There are three trigger sources internal exte...

Page 65: ...sub multipleofsampleclockissentto theTrigger Out TriggerCompare Thetrigger inputconditionhasbeensatisfied butnotnecessarily triggered e g thetrigger enablewasnotasserted SelfTrigger SeeSelftrigger mod...

Page 66: ...hen terminated on 50 The maximum output current capability is 15 mA As the output is retro terminated it is possible to drive a 50 line un terminated HiZ without loss of performance Figure 5 2 Trigger...

Page 67: ...sitionisongoing AVG IO 3only Out LowLevel Level Fixed low levelsignalfor debugpurposes Out HighLevel Level Fixed high levelsignalfor debugpurposes Table 5 3 List of signals selectable for the programm...

Page 68: ...ll typically give 1 6 V into 50 As can be seen in the diagram below the 3 3 V output buffer has a 50 resistor in series Therefore the available output high level voltage will depend on the load applie...

Page 69: ...ollowing development environments Visual C Visual C CLI Visual Basic NET Driver API documentation The AqMD3 APIdocumentation can also be accessed from IVI C Start Acqiris MD3 Documentation AqMD3 C IVI...

Page 70: ...rary lib must be referenced This section demonstrates usage of the driver using instrument specific references All IVI C driver programs must do the following include AqMD3 h Link to AqMD3 lib Prefix...

Page 71: ...set VI_FALSE Setup IVI defined initialization options ViConstString standardInitOptions Cache true InterchangeCheck false QueryInstrStatus true RangeCheck true RecordCoercions false Simulate false sta...

Page 72: ...from MD2 2 x to MD3 3 x Please refer to the following documents for guidelines accessible from Start Acqiris MD3 Documentation or from C Program Files Acqiris MD3 Documentation AgMD2 to AqMD3 IVI C So...

Page 73: ...ter Bypass false Bydefault thebandwidthlimiter isdisable Verticalrange 2 5 Volts Verticaloffset 0 Volts Verticalcoupling DC Trigger source Internal1 Trigger delay 0 ns Trigger type Edge Trigger coupli...

Page 74: ...perform an implicit ApplySetup before the actual action Actions with implicit ApplySetup Method name Description SelfTest Toinsurethemoduleisactuallyinthedesiredstatebeforedoingtheselftest SelfCalibr...

Page 75: ...77 7 3 How to access repeated capabilities 80 7 4 How to generate a software trigger 81 7 5 How to enable or bypass the bandwidth limiter 82 7 6 How to set the external trigger 83 7 7 How to perform b...

Page 76: ...the PXI instruments on user system and get their VISA addresses include stdio h include visa h int main ViSession rm VI_NULL viOpenDefaultRM rm ViChar search PXI INSTR ViFindList find VI_NULL ViUInt3...

Page 77: ...on The smart calibration implemented in MD3 drivers allows to save time by automatically keeping in memory the calibration information from any self calibration performed since the beginning of the se...

Page 78: ...rate Onlythe1sttime for anidenticalsetofparameter values Channelparameters Verticalrange Inputfilter Bypass Yes No CalibrationTargetVoltage OnlyifCalibration TargetVoltageEnabledistrue Andeachtimethis...

Page 79: ...7 2 How to calibrate the module Acqiris SA230E User s Manual 79 IVI NET Interface Method Property name IAqMD3Calibration IsRequired SelfCalibrate...

Page 80: ...PGA DataLink Notsupported LogicDeviceMemoryBank Notsupported MonitoringValue Theseparametersarefor informationonlyor canbeusedfor debuggingpurpose ThereareaccessiblethroughtheMD3SFPor thecommandbelow...

Page 81: ...ftwareTrigger IVI C or to method IAqMD3Trigger SendSoftwareTrigger IVI NET sends a single software trigger SendSoftwareTrigger must be called as many times as required Multi record acquisitions requir...

Page 82: ...R_INPUT_FILTER_BYPASS VI_TRUE Using the AqMD3 IVI NET driver driver Channels L Channel1 Filter Bypass true Selecting the filter frequency User can select the desired the Max frequency by setting Chann...

Page 83: ...VI C AqMD3_SetAttributeViString session AQMD3_ATTR_ACTIVE_TRIGGER_SOURCE External1 AqMD3_SetAttributeViReal64 session External1 AQMD3_ATTR_TRIGGER_LEVEL level IVI NET spDriver Trigger ActiveSource Ext...

Page 84: ...ease refer to section for more information Using the AqMD3 IVI C driver To use the binary decimation and set the sample rate to a lower value use the AQMD3_ATTR_ SAMPLE_RATE attribute sampleRate 200e6...

Page 85: ...User s Manual 85 7 8 How to load a new firmware The on board FPGAs field programmable gate arrays contain processor logic needed to efficiently execute several crucial functions They will be automatic...

Page 86: ...10 mV amplitude are acquired at 100 kHz from a signal generator using the external trigger 1 Set the range and configure the offset such as the full baseline is visible in the trace Note that if the...

Page 87: ...ilization parameters Pulse Polarity Pulse Threshold and Digital Offset with the SFP and once the parameters are determined you can configure the baseline stabilization in your application From the pre...

Page 88: ...BASELINE_ CORRECTION_PULSE_THRESHOLD pulseThreshold checkApiCall AqMD3_SetAttributeViInt32 session Channel1 AQMD3_ATTR_CHANNEL_BASELINE_ CORRECTION_PULSE_POLARITY pulsePolarity checkApiCall AqMD3_SetA...

Page 89: ...ce signal with reference signal expected values This utility checks the version of control FPGA firmware already loaded If necessary it pro poses to update the firmware using the Firmware Update Utili...

Page 90: ...rify 90 Acqiris SA230E User s Manual When the version of control FPGA firmware is updated and successful please power off your computer restart it again for the update to take effect and process AqMD3...

Page 91: ...is close to an integer We could therefore round down to Ncycles 901 and we would get Fin 43 994140625 MHz which is an input frequency that satisfies coherent sampling The integer number should be cho...

Page 92: ...perating conditions This parameter is provided for information only 9 3 Q What happens if the host processor goes in hibernation mode A Hibernation while the ADC module is in operation is not supporte...

Page 93: ...roducts Only properly trained service personnel may perform installation and service procedures Operator is responsible to maintain safe operating conditions To ensure safe operating conditions module...

Page 94: ...move power from the entire test system and discharge any capacitors before connecting or disconnecting cables or jumpers installing or removing ADC modules or making internal changes such as installin...

Page 95: ...ark of the European Community Australian Communication and Media Authority mark to indicate regulatory compliance as a registered supplier This symbol indicates product compliance with the Canadian In...

Page 96: ...discharge ESD ESD can damage the highly sensitive components in your module ESD damage is most likely to occur as the module is being installed or when cables are connected or disconnected Protect th...

Page 97: ...formation and reference material specific toyour ADC moduleproduct Data Sheet In addition to a detailed product introduction the data sheet suppliesfullproductspecifications Soft Front Panel help syst...

Page 98: ...This information is subject to change without notice Acqiris SA 2018 2019 Tuesday August 27 2019 Switzerland www acqiris com...

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