46
D9
Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.
Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing
SMRAM.
DA
Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel).
See POST Code Checkpoints section of document for more information.
E1-E8
EC-EE
OEM memory detection/configuration error. This range is reserved for chipset vendors &
system manufacturers. The error associated with this value may be different from one platform
to the next.
Bootblock Recovery Code Checkpoints
Checkpoint
Description
E0
Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA
controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9
Set up floppy controller and data. Attempt to read from floppy.
EA
Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB
Disable ATAPI hardware. Jump back to checkpoint E9.
EF
Read error occurred on media. Jump back to checkpoint EB.
F0
Search for pre-defined recovery file name in root directory.
F1
Recovery file not found.
F2
Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3
Start reading the recovery file cluster by cluster.
F5
Disable L1 cache.
FA
Check the validity of the recovery file configuration to the current configuration of the flash
part.
FB
Make flash write enabled through chipset and OEM specific method. Detect proper flash part.
Verify that the found flash part size equals the recovery file size.
F4
The recovery file size does not equal the found flash part size.
FC
Erase the flash part
FD
Program the flash part.
FF
The flash has been updated successfully. Make flash write disabled. Disable ATAPI
hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
POST Code Checkpoints
Checkpoint
Description
03
Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime
data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS
as mentioned in the Kernel Variable "wCMOSFlags."
Summary of Contents for Veriton Hornet N260G
Page 10: ...4 M B Placement ...
Page 11: ...5 Block Diagram ...
Page 46: ...40 Remove CPU Cooler Process 1 Release the four screws 2 Remove CPU cooler ...
Page 72: ...66 USB CONNECTORS Stacked Black REAR_USB1 REAR_USB2 LAN1 ...
Page 74: ...68 AUDIO2 LINE OUT Lime in Color DCIN ...
Page 75: ...69 VGA D SUB ...
Page 76: ...70 HDMI ...
Page 77: ...71 ...
Page 78: ...72 SATA CONN ...
Page 79: ...73 Card reader ...
Page 80: ...74 ...
Page 81: ...75 PS2 combo port ...
Page 83: ...77 Exploded Diagram ...
Page 84: ...78 ...