A
A
B
B
C
C
D
D
E
E
1
1
2
2
3
3
4
4
Buffered reset to CPU
Follow DG 1.5 & Tacoma_Fall2 1.0
Use open drain logic gate:
+1.05VS_VTT PU pop 75ohm
series resister pop 43ohm
reserve
XBOX
三
三
三
三三
三
三
三三
三
三
三三
三
三
三
偵
偵
偵
偵偵
偵
偵
偵
CPU
有
有
有
有有
有
有
有有
有
有
有有
有
有
有
RESET#:
都
都
都
都
ok
後
後
後
後後
後
後
後
CPU
做
做
做
做
reset
PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS
PCH->CPU
UNCOREPWRGOOD:
非
非
非
非
CORE
外
外
外
外外
外
外
外外
外
外
外
OK
SM_DRAMPWROK:DRAM power ok
RESET#:
都
都
都
都
ok
後
後
後
後後
後
後
後
CPU
做
做
做
做
reset
DDR3 Compensation Signals
Use open drain logic gate:
+1.5V_CPU_VDDQ PU pop 200ohm
series resister pop 130ohm
follow Checklist 1.5
Follow DG 1.5 & Tacoma_Fall2 1.0
SM_DRAMPWROK:DRAM power ok
UNCOREPWRGOOD:
非
非
非
非
CORE
外
外
外
外外
外
外
外外
外
外
外
OK
Follow DG 1.5& Tacoma_Fall2 1.0
SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil
SM_RCOMP2
W=15mil L=500mil S=13mil
Checklist1.5 P.67 Graphis Disable Guide
eDP disable:
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PU 1K_5% to +1.05VS_VTT
0921 LVDS@->@
Tacoma_Fall2 1.0 PU 1K +3VS
Check list 1.5 PU 1K +3VS
Debug port DG1.1-1.3 50~5K ohm
12/22 Add(ESD request)
XDP_TDI
XDP_TDO
BUF_CPU_RST#
PM_SYS_PW RGD_BUF
H_CATERR#
CLK_CPU_DPLL#
CLK_CPU_DPLL
H_CPUPW RGD_R
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_DBRESET#
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
BUFO_CPU_RST#
H_CPUPW RGD
H_PROCHOT#_R
H_PROCHOT#
PM_DRAM_PW RGD_R
PLT_RST#
PM_DRAM_PW RGD_R
BUF_CPU_RST#
SM_DRAMRST#
H_PECI
CLK_CPU_DPLL
CLK_CPU_DPLL#
XDP_DBRESET#
H_CPUPW RGD_R
+1.05VS_VTT
+1.5V_CPU_VDDQ
+1.05VS_VTT
+3VALW
+3VS
+1.05VS_VTT
+3VS
H_SNB_IVB#
<17>
H_PECI
<18,29>
H_PROCHOT#
<29,35>
H_THRMTRIP#
<18>
H_PM_SYNC
<15>
H_CPUPW RGD
<18>
PLT_RST#
<17>
SYS_PW ROK
<15>
PM_DRAM_PW RGD
<15>
CLK_CPU_DMI
<14>
CLK_CPU_DMI#
<14>
CLK_CPU_DPLL
<14>
CLK_CPU_DPLL#
<14>
SM_DRAMRST#
<6>
XDP_DBRESET#
<15>
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PROCESSOR(3/7) DDRIII
Custom
5
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PROCESSOR(3/7) DDRIII
Custom
5
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PROCESSOR(3/7) DDRIII
Custom
5
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
R17
1K_0402_5%
1
2
T6
PAD
@
C66
0.1U_0402_16V4Z
1
2
R10
25.5_0402_1%
1
2
R8
56_0402_5%
1
2
R14
0_0402_5%
@
1
2
R9
140_0402_1%
1
2
R13
0_0402_5%
1
2
R15
43_0402_1%
1
2
R5
1K_0402_5%
LVDS@ 1
2
CLOCKS
MISC
THERMAL
PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
UCPU1B
IVY-BRIDGE_BGA1023
C867@
SM_RCOMP[1]
BE43
SM_RCOMP[2]
BG43
SM_DRAMRST#
AT30
SM_RCOMP[0]
BF44
BCLK#
H2
BCLK
J3
DPLL_REF_CLK#
AG1
DPLL_REF_CLK
AG3
CATERR#
C49
PECI
A48
PROCHOT#
C45
THERMTRIP#
D45
SM_DRAMPWROK
BE45
RESET#
D44
PRDY#
N53
PREQ#
N55
TCK
L56
TMS
L55
TRST#
J58
TDI
M60
TDO
L59
DBR#
K58
BPM#[0]
G58
BPM#[1]
E55
BPM#[2]
E59
BPM#[3]
G55
BPM#[4]
G59
BPM#[5]
H60
BPM#[6]
J59
BPM#[7]
J61
PM_SYNC
C48
PROC_DETECT#
C57
PROC_SELECT#
F49
UNCOREPWRGOOD
B46
C67
0.1U_0402_16V4Z
1
2
T4
PAD
@
R4
1K_0402_5%
LVDS@ 1
2
T1
PAD
@
T5
PAD
@
C476
180P_0402_50V8J
@
1
2
R7
62_0402_5%
1
2
R11
200_0402_1%
1
2
R16
200_0402_5%
1
2
C65
0.1U_0402_16V4Z
@
1
2
U1
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y
4
P
5
R6
10K_0402_5%
1
2
R18
130_0402_5%
1
2
U2
MC74VHC1G09DFT2G_SC70-5
B
1
A
2
Y
4
V
C
C
5
G
3
T3
PAD
@
T2
PAD
@
R12
75_0402_5%
1
2
