Acer Q1VZC, Schematics Document

Page: 20 / 45

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VCC3_3 = 178mA detal waiting for newest spec
VCCDMI = 47mA detal waiting for newest spec
3mA
65mA
1mA
803mA
1mA
75mA
75mA
55mA
95mA
2mA
10mA Need +3VALW and 0.1U close PCH
Near P32
Place near
AA16,W16 Place near
T34 Place near
AJ2
Not support Deep S4,S5
connect to +3VALW
suppied by internal
1.05V VR must NC
+1.05V analog
internal clock PLL
Can NC
Place
near AG33
Place
near BJ8
suppied by internal
1.05V VR Must NC
Near T24 Near T23
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
GPIO28
On-Die PLL Voltage Regulator
H
： ： ： ：
On-Die PLL voltage regulator
enable
suppied by internal
1.05V VR Must NC
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
GPIO28
On-Die PLL Voltage Regulator
H
： ： ： ：
On-Die PLL voltage regulator
enable
Place
near AF33,
AF34,AG34
Place
near AF17
isolation between SSC (AG33)
and DIFFCLKN(AF33,AF34,AG34)
18mil width(DIFFCLKN)
10mil (SSC)
Near T16
Near T38
Near AA19
Near M6
Near V16
Near A22
Near AC16
Near AH13,AH14,AF13
Near N20
Near P34
Near N26
Near M26
Near BD47
Near BF47
SGA20331E10
330U 2V H1.9
9mohm POLY
20mil
For Deep S3 turn off +V5RVCCSUS3_3
+VCCA_USBSUS
+3VS_VCC_CLKF33
+VCCDSW3_3
+3VS_VCC_CLKF33
+VCCSUS1
+VCCACLK
+VCCRTCEXT
+VCCSST
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCSATAPLL
+VCCAPLL_CPY_PCH
+PCH_VCCDSW
+1.05VM_VCCSUS
+PCH_V5REF_RUN
+PCH_V5REF_SUS
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCDSW3_3
PCH_PWR_EN#
+1.05VS_VTT
+1.05VS_VTT
+3VS
+1.05VS_VTT
+VCCSUS3_3
+1.05VS_VTT
+VCCSUS3_3
+3VS
+1.05VS_VTT
+RTCVCC
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+5VREF_SUS
+3VS +5VS
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+VCCSUS3_3
+5VALW
+5VREF_SUS
+1.05VS_VTT
+1.5VS
+1.5VS
+3VALW_PCH
+VCCSUS3_3
+VCCSUS3_3
+VCCSUS3_3
+3VALW
PCH_PWR_EN# <25,33>
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PCH (8/9) PWR
Custom
20 45 Friday, April 20, 2012
2011/11/22 2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PCH (8/9) PWR
Custom
20 45 Friday, April 20, 2012
2011/11/22 2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
PCH (8/9) PWR
Custom
20 45 Friday, April 20, 2012
2011/11/22 2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
C
2
1
1
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C
2
1
2
1
U
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0
4
0
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6
.3
V
6
K
1
2
C
2
2
9
0
.1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C221 0.1U_0402_16V7K
1 2
T28
PAD @
R243
100_0402_5%
1
2
C
2
1
3
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
R
2
8
8
2
0
K
_
0
4
0
2
_
5
%
1
2
C227
1U_0402_6.3V6K
1
2
C
2
3
0
0
.1
U
_
0
4
0
2
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1
6
V
7
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1
2
C219
0.1U_0402_16V7K
1
2
C
2
3
2
0
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U
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4
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1
6
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7
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1
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2
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9
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U
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4
0
2
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1
6
V
7
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1
2
R553
1K_0402_5%
1
2
C
2
0
5
0
.1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
T26 PAD @
T29 PAD @
R242 0_0402_5%
1 2
Q68
AP2301GN-HF_SOT23-3
DS3@
2
3 1 T24 PAD @
C
2
0
9
2
2
U
_
0
8
0
5
_
6
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V
6
M
1
2
C200
10U_0603_6.3V6M
1
2
D4
RB751V-40_SOD323-2
1
2
C218
0.1U_0402_16V7K
1
2
T27 PAD @
J13
JUMP_43X39
@
1
1
2
2
C
2
3
1
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
R240
0_0603_5%
S3@
1 2
POWER
SATA
USB
Clock and Miscellaneous
HDA
CPU
RTC
PCI/GPIO/LPC
MISC
U16J
COUGARPOINT_FCBGA989
HM77@
DCPSUSBYP
V12
VCCASW[1]
AA19
VCCASW[2]
AA21
VCCASW[3]
AA24
VCCASW[5]
AA27
VCCASW[6]
AA29
VCCSUSHDA
P32
VCCSUS3_3[6]
P24
VCCIO[34]
T26
VCCIO[4]
AD17
VCCASW[7]
AA31
VCCASW[8]
AC26
VCCASW[9]
AC27
VCCASW[10]
AC29
VCCASW[11]
AC31
VCCASW[12]
AD29
V5REF
P34
VCC3_3[4]
T34
VCCRTC
A22
VCCSUS3_3[10]
V24
VCCSUS3_3[9]
V23
VCCSUS3_3[8]
T24
VCCSUS3_3[7]
T23
VCCIO[2]
AC16
VCCADPLLB
BF47
VCCIO[8]
AF33
V5REF_SUS
M26
VCCIO[3]
AC17
DCPSUS[1]
T17
VCCIO[10]
AG33
VCCADPLLA
BD47
VCCVRM[4]
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW[4]
AA26
VCCIO[9]
AF34
VCCIO[7]
AF17
DCPSST
V16
VCCIO[5]
AF13
VCCASW[22]
T21
VCCASW[23]
V21
VCCASW[21]
T19
VCC3_3[1]
AA16
VCC3_3[8]
W16
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
VCCIO[29]
N26
VCCIO[30]
P26
VCCIO[31]
P28
VCCIO[32]
T27
V_PROC_IO
BJ8
VCCIO[33]
T29
VCCIO[11]
AG34
VCCASW[13]
AD31
VCCASW[14]
W21
VCCASW[15]
W23
VCCASW[16]
W24
VCCASW[17]
W26
VCCASW[18]
W29
VCCASW[19]
W31
VCCASW[20]
W33
VCCIO[6]
AF14
VCCVRM[1]
AF11
VCCIO[12]
AH13
VCCIO[13]
AH14
VCC3_3[2]
AJ2
VCCAPLLSATA
AK1
DCPSUS[3]
AL24
VCCIO[14]
AL29
DCPSUS[4]
AN23
VCCSUS3_3[1]
AN24
VCCAPLLDMI2
BH23
DCPSUS[2]
V19
VCCDSW3_3
T16
VCC3_3[5]
T38
C
2
0
1
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C220
0.1U_0402_16V7K
1
2
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2
4
1
2
0
K
_
0
4
0
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%
1
2
C
2
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0
1
U
_
0
4
0
2
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6
.3
V
6
K
1
2
L4
10UH_LB2012T100MR_20%
1 2
C207
0.1U_0402_16V7K
1 2
D3
RB751V-40_SOD323-2
1
2
Q8
AP2301GN-HF_SOT23-3
DS3@
2
3 1
C206
0.1U_0402_16V7K
1
2
C204
1U_0402_6.3V6K
1
2
C499
0.1U_0402_16V7K
1 2
C500
0.1U_0402_16V7K
1 2
T30 PAD @
C215
1U_0402_6.3V6K
1
2
C214
1U_0603_10V6K
1
2
T25 PAD @
C202
0.1U_0402_16V7K
1
2
R552
1K_0402_5%
1
2
+
C216
330U_D2_2V_Y
@
1
2
C234
0.1U_0402_16V4Z
1
2
C203
0.1U_0402_16V7K
1
2
C224
1U_0402_6.3V6K
1
2
C226 0.1U_0402_16V7K
1 2
C
2
3
3
0
.1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
L3
10UH_LB2012T100MR_20%
1 2
C222
1U_0402_6.3V6K
1
2
L5
10UH_LB2012T100MR_20%
1 2
C225
1U_0402_6.3V6K
1
2
C223
1U_0402_6.3V6K
1
2
C
2
1
7
1
U
_
0
4
0
2
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6
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V
6
K
1
2
C
2
0
8
2
2
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_
0
8
0
5
_
6
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V
6
M
1
2
C
2
2
8
4
.7
U
_
0
6
0
3
_
6
.3
V
6
K
1
2
R244
100_0402_5%
1
2