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Acer AcerNote Light 370P, Service Manual

The Acer AcerNote Light 370P is a versatile laptop designed for on-the-go professionals. Enhance your experience with its powerful performance and user-friendly features. Enjoy the convenience of having a comprehensive User Manual available for free download from manualshive.com, providing you with the necessary information to maximize its potential.

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Major Chips Description

2-83

Table 2-14

NS87336VJG Pin Descriptions (continued)

Pin

No.

I/O

Description

IORCHDY

51

O

I/O Channel Ready.  When IORCHDY is driven low, the EPP extends
the host cycle.

IRQ3, 4
IRQ5-7
IRQ9-11
IRQ12, 15
(PnP Mode)

99, 98
96-94,
55-57,
66, 58

I/O

Interrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15.  This pin can be a totem-
pole output or an open-drain output.  The interrupt can be sourced by
one of the following: UART1 and/or UART2, parallel port, FDC,
SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.

IRQ5 is multiplexed with ADRATE0.

IRQ12 is multiplexed with /DSR2 and IRRX2.

IRQ15 is multiplexed with SIRQI1.

IRQ3, 4
(Legacy Mode)

99, 98

O

Interrupt 3 and 4.  These are active high interrupts associated with
the serial ports.  IRQ3 presents the signal if the serial channel ahs
been designated as COM2 or COM4.  IRQ4 presents the signal if the
serial port is designated as COM1 or COM3.  The interrupt is reset
low (inactive ) after the appropriate interrupt service routine is
executed.

IRQ5
(Legacy Mode)

96

I/O

Interrupt 5.  Active high output that indicates a parallel port interrupt.
When enabled, this pin follows the /ACK signal input.  When it is noe
enabled, this signal is tri-state.  This pin ia I/O only when ECP is
enabled, and IRQ5 is configured.

IRQ6
(Legacy Mode)

95

O

Interrupt 6.  Active high output to signal the completion of the
execution phase for certain FDC commands.  Also used to signal
when a data transfer is ready during a non-DMA operation.

IRQ7
(Legacy Mode)

94

I/O

Interrupt 7.  Active high output that indicates a parallel port interrupt.
When enabled, this signal follows the /ACK signal intput.  When it is
not enabled, this signal is tri-state.  This pin is I/O only when ECP is
enabled, and IRQ7 is configured.

IRRX1
IRRX2

65, 66

I

IrDA or SHARP- Infrared Receive.  One of these pins is the infrared
serial data input.

IRRX1 is multiplexed with SIN2.

IRRX2 is multiplexed with /DSR2 and IRQ12.

IRTX

63

O

Infrared Transmit. Infrared serial data output.  Software configuration
selects either IrDA or Sharp-IR protocol.

This pin is multiplexed with SOUT2/BOUT/CFG0.

MR

100

I

Master Reset.  Active high output that resets the controller to the idle
state and resets all disk interface outputs to their inactive states.  The
DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values.  The
Specify command parameters are not affected

Summary of Contents for AcerNote Light 370P

Page 1: ...TI Extensa 61X Series AcerNote 370P Notebook Service Guide PART NO 2238309 0809 DOC NO PRINTED IN USA ...

Page 2: ... is Should the programs prove defective following their purchase the buyer and not Acer Incorporated its distributor or its dealer assumes the entire cost of all necessary servicing repair and any incidental or consequential damages resulting from any defect in the software Further Acer Incorporated reserves the right to revise this publication and make changes from time to time in the contents he...

Page 3: ...ter 2 Major Chip Descriptions This chapter lists the major chips used in the notebook and includes pin descriptions and related diagrams of these chips Chapter 3 BIOS Setup Information This chapter includes the system BIOS information focusing on the BIOS setup utility Chapter 4 Disassembly and Unit Replacement This chapter tells how to disassemble the notebook and replace components Appendix A Mo...

Page 4: ...scription and general operating instructions M1521 M1523 and M7101 Data Sheets contain information on the Acer chips C T 65550 Data Sheet contains detailed information on the Chips Tech VGA controller TI PCI1131 Data Sheet contains detailed information on the Texas Instrument PCMCIA controller NS87336VJG Data Sheet contains detailed information on the NS super I O controller YMF715 Data Sheet cont...

Page 5: ...ces of additional information related to the current topic WARNING Alerts you to any damage that might result from doing or not doing specific actions CAUTION Gives precautionary measures to avoid possible hardware or software problems IMPORTANT Reminds you to do specific actions relevant to the accomplishment of procedures TIP Tells how to accomplish a procedure with minimum steps through little ...

Page 6: ...vi ...

Page 7: ...on Board PCB No 96465 1 1 11 1 3 Jumpers and Connectors 1 12 1 4 Hardware Configuration and Specification 1 14 1 4 1 Memory Address Map 1 14 1 4 2 Interrupt Channel Map 1 14 1 4 3 DMA Channel Map 1 15 1 4 4 I O Address Map 1 15 1 4 5 M7101 GPIO General Purpose I O Port Definition 1 16 1 4 6 Processor 1 16 1 4 7 BIOS 1 17 1 4 8 System Memory 1 17 1 4 9 Second Level Cache 1 18 1 4 10 Video Memory 1 ...

Page 8: ...30 1 5 1 2 MultiBoot 1 31 1 5 1 3 Power Management 1 31 1 5 2 Drivers Applications and Utilities 1 36 1 6 System Block Diagram 1 38 1 7 Environmental Requirements 1 39 1 8 Mechanical Specifications 1 40 Chapter 2 Major Chips Description 2 1 Major Component List 2 1 2 2 ALI M1521 2 2 2 2 1 Features 2 2 2 2 2 Block Diagram 2 4 2 2 3 System Architecture 2 5 2 2 4 Data Path 2 6 2 2 5 Pin Diagram 2 7 2...

Page 9: ... Pin Descriptions 2 43 2 6 TI PCI1131 CardBus Controller 2 56 2 6 1 Overview 2 56 2 6 2 Architecture 2 57 2 6 3 Features 2 57 2 6 4 Block Diagram 2 59 2 6 5 Pin Diagram 2 61 2 6 6 Terminal Functions 2 63 2 7 NS87336VJG Super I O Controller 2 75 2 7 1 Features 2 75 2 7 2 Block Diagram 2 77 2 7 3 Pin Diagram 2 78 2 7 4 Pin Description 2 79 2 8 Yamaha YMF715 Audio Chip 2 87 2 8 1 Features 2 87 2 8 2 ...

Page 10: ...ctrical Specifications 2 102 2 11 2 Pin Connector Assignment 2 103 2 11 3 Top Overlay 2 104 2 11 4 Bottom Overlay 2 104 2 12 T62 066 C DC AC Inverter 12 1 2 105 2 12 1 Electrical Specifications 2 105 2 12 2 Pin Connector Assignment 2 106 2 12 3 Top Overlay 2 107 2 12 4 Bottom Overlay 2 107 Chapter 3 BIOS Setup Information 3 1 When to Use Setup 3 1 3 2 Entering Setup 3 2 3 3 Basic System Configurat...

Page 11: ...mer 3 11 3 5 3 Hard Disk Standby Timer 3 11 3 5 4 System Sleep Timer 3 12 3 5 5 System Sleep Mode 3 12 3 5 6 System Resume Timer Mode 3 12 3 5 7 System Resume Date and Time 3 12 3 5 8 Modem Ring Resume On Indicator 3 12 3 5 9 Battery low Warning Beep 3 13 3 5 10 Sleep Upon Battery low 3 13 3 6 System Information Reference 3 14 3 7 Load Setup Default Settings 3 16 Chapter 4 Disassembly and Unit Rep...

Page 12: ... the Top Cover 4 14 4 5 6 Removing the Base Assembly 4 16 4 5 7 Removing the Motherboard 4 17 4 5 8 Disassembling the Motherboard 4 20 4 5 9 Removing the Touchpad 4 21 4 6 Disassembling the Display 4 22 Appendix A Model Number Definition Appendix B Exploded View Diagram Appendix C Spare Parts List Appendix D Schematics Appendix E BIOS POST Checkpoints Appendix F Technical Bulletins and Updates App...

Page 13: ...1 12 Keyboard Connection Board Layout Bottom Side 1 11 1 13 Jumpers and Connectors Top View 1 12 1 14 Power Management Block Diagram 1 31 1 15 System Block Diagram 1 38 2 1 Alladin III Block Diagram 2 4 2 2 Alladin III System Architecture 2 5 2 3 M1521 Data Path 2 6 2 4 M1521 Pin Diagram 2 7 2 5 M1523 Block Diagram 2 16 2 6 M1523 Pin Diagram 2 17 2 7 M7101 Pin Diagram 2 25 2 8 State Machine for PC...

Page 14: ...ectors With Locks 4 3 4 3 Disassembly Sequence Flowchart 4 5 4 4 Removing the Memory Door 4 6 4 5 Installing and Removing Memory 4 6 4 6 Removing the Hard Disk Drive Bay Cover 4 7 4 7 Removing the Hard Disk Drive 4 8 4 8 Removing the Display Hinge Covers 4 9 4 9 Unplugging the Keyboard Connectors 4 9 4 10 Removing the Heat Sink Assembly Screws 4 10 4 11 Removing the Internal Drive 4 11 4 12 Replac...

Page 15: ...e PC Card Slot Unit 4 20 4 25 Removing the Keyboard Connection Board 4 20 4 26 Removing the Touchpad 4 21 4 27 Removing the LCD Bumpers 4 22 4 28 Removing the Display Bezel Screws 4 22 4 29 Removing the Display Bezel 4 23 4 30 Removing the Hinge Cable Cover 4 23 4 31 Removing the LCD Panel 4 24 4 32 Removing the LCD 4 24 4 33 Removing the DC AC Inverter and LCD ID Inverter Boards 4 25 4 34 Removin...

Page 16: ...01 GPIO Port Definition 1 16 1 12 Processor Specifications 1 16 1 13 BIOS Specifications 1 17 1 14 Memory Configurations 1 18 1 15 Video RAM Configuration 1 19 1 16 Video Hardware Specification 1 19 1 17 Supported External CRT Resolutions 1 19 1 18 Supported LCD Resolutions 1 20 1 19 Parallel Port Configurations 1 21 1 20 Serial Port Configurations 1 21 1 21 Audio Specifications 1 22 1 22 PCMCIA S...

Page 17: ...1 40 Location of Drivers in the System Utility CD 1 36 1 41 Location of Applications in the System Utility CD 1 36 1 42 Environmental Requirements 1 38 1 43 Mechanical Specifications 1 39 2 1 Major Chips List 2 1 2 2 M1521 Signal Descriptions 2 8 2 3 M1523 Signal Descriptions 2 18 2 4 M7101 Pin Descriptions 2 26 2 5 M7101 Different Pin Definition Setting 2 34 2 6 M7101 Original Pin Definition Sett...

Page 18: ...Description 2 103 2 23 Pin Description 2 103 2 24 MAXIMUM RATINGS 2 105 2 25 Electrical Characteristics 2 105 2 26 J1 52103 1217 MOLEX Pin Description 2 106 2 27 J2 SM02 8 0 B BHS 1 TB2P JST Pin Description 2 106 3 1 Display Device Settings 3 5 3 2 Floppy Disk Drive Control Settings 3 6 3 3 Hard Disk Drive Control Settings 3 6 3 4 System Boot Drive Control Settings 3 7 3 5 CD ROM Image Description...

Page 19: ...ction System Introduction 1 1 This chapter introduces the notebook its features components and specifications 1 1 Overview The notebook was designed with the user in mind The figure below shows the notebook with the display open Figure 1 1 Notebook ...

Page 20: ...um Ion or Nickel Metal Hydride battery pack Power management system with standby and hibernation power saving modes Multimedia 16 bit stereo audio with software wavetable Built in dual speakers Ultra slim high speed CD ROM drive1 Human centric Design and Ergonomics Lightweight and slim Sleek smooth and stylish design Full sized keyboard Wide and curved palm rest Centrally located touchpad pointing...

Page 21: ...rophone in Port External 3 5mm minijack condenser microphone 3 Line in Port Line in device e g CD player stereo walkman 4 Line out Port Line out device e g speakers headphones 5 External Floppy Drive Connector External floppy drive 6 Serial Port Serial device e g serial mouse 7 Parallel Port Parallel device e g parallel printer 8 External CRT port Monitor up to 1024x768 256 colors 9 PS 2 Port PS 2...

Page 22: ...ower Switch Condition Green On Charged battery is installed or a power AC adapter is connected to the notebook Red Off Battery is installed and a powered AC adapter is connected to the notebook and charging the battery rapid charge mode Orange On Battery is installed and a powered AC adapter is connected to the notebook and charging the battery charge in use mode Flashing On Battery is running low...

Page 23: ...ltra VGA monitor LCD projection panel Video PCI local bus video with graphics accelerator and 1MB video RAM Audio 16 bit stereo audio built in dual speakers separate audio ports Keyboard and pointing device 84 85 88 key with Windows 95 keys Touchpad centrally located on palmrest 101 102 key PS 2 compatible keyboard or 17 key numeric keypad External serial or PS 2 mouse or similar pointing device I...

Page 24: ...ttery 2 6 kg 5 7 lbs 2 8 kg 6 2 lbs Dimensions main footprint W x D x H 306mm x 228mm x 46mm 12 05 x 8 98 x 1 81 Temperature Operating Non operating 10ºC 35ºC 20ºC 60ºC Humidity Operating Non operating non condensing 20 80 20 80 AC adapter 100 240 Vac 50 60 Hz 45W autosensing AC adapter Extra AC adapter Battery pack Lithium Ion 4 5 hr rapid charge 6 8 hr charge in use Extra battery pack External b...

Page 25: ...System Introduction 1 7 1 2 System Board Layout 1 2 1 Main Board PCB No 96149 SC Figure 1 4 Main Board Layout Top Side Note This switch setting is not for Extensa 610 use ...

Page 26: ...1 8 Service Guide Figure 1 5 Main Board Layout Bottom Side ...

Page 27: ...o Connection Board PCB No 96467 1 Figure 1 6 Audio Connection Board Layout Top Side 1 2 3 Battery Connection Board PCB No 95498 1 Figure 1 7 Battery Connection Board Layout Top Side Figure 1 8 Battery Connection Board Layout Bottom Side ...

Page 28: ...1 10 Service Guide 1 2 4 HDD Connection Board PCB No 96463 1 Figure 1 9 HDD Connection Board Layout Top Side Figure 1 10 HDD Connection Board Layout Bottom Side ...

Page 29: ...System Introduction 1 11 1 2 5 Keyboard Connection Board PCB No 96465 1 Figure 1 11 Keyboard Connection Board Layout Top Side Figure 1 12 Keyboard Connection Board Layout Bottom Side ...

Page 30: ...N15 HDD Connector CN5 External floppy drive port CN16 Keyboard connector CN6 LCD Connector CN17 CD ROM connector CN7 Audio speaker connector left CN18 Battery pack connector CN8 LCD cover switch connector CN19 Track Point Board Connector CN9 Fan connector S1 CPU Voltage Setting CN10 Audio speaker connector right SW2 Function Setting CN11 Charger Connector SW3 CPU Speed Setting Figure 1 13 Jumpers ...

Page 31: ... Off Off On Table 1 5 CPU Speed SW3 Settings CPU Speed 120MHz 133MHz 150MHz Switch 1 Off On Off Switch 2 On Off On Switch 3 Off Off On Switch 4 On On On Table 1 6 Multi Function Switch SW2 Settings Switch ON OFF 1 Keyboard Type Default OFF 2 Keyboard Type 88 key Japan keyboard 84 85 key U S keyboard 3 Password Bypass Check 4 Generic boot up screen show on screen in POST No Yes ...

Page 32: ...urce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SMI NMI IRQ 0 IRQ 1 IRQ 2 IRQ 8 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 13 IRQ 14 IRQ 15 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 Power management unit Parity error detected I O channel error Interval timer counter 0 output Keyboard Interrupt from controller 2 cascade Real time clock Cascaded to INT 0AH IRQ 2 Audio option PCMCIA Audio option PCMCIA PS 2 mouse INT from co...

Page 33: ...F8 2FF 378 37A 3BC 3BE 3B4 3B5 3BA 3C0 3C5 3C6 3C9 3C0 3CF 3D0 3DF 3E0 3E1 3E8 3EF 3F0 3F7 3F8 3FF CF8 CFF DMA controller 1 Interrupt controller 1 Timer 1 Timer 2 Keyboard controller 38802 chip select Real time clock and NMI mask DMA page register Interrupt controller 2 DMA controller 2 CD ROM M7101 registers Hard disk select Audio option default Audio option Audio option Audio option Parallel por...

Page 34: ...sable 12V for flash ROM 1 Enable 12V for flash ROM Register E0h bit 10 0 3 mode FDD 1 Normal Register E0h bit 11 Thermal sensor clock line Register E0h bit 12 Thermal sensor reset Register E0h bit 13 0 Enable battery LED 1 Disable battery LED Register E0h bit 14 0 Disable audio amplifier 1 Enable audio amplifier Register E1h bit 0 0 NiMH battery 1 Li ion battery Register E1h bit 1 CPU thermal high...

Page 35: ... employing 8 16 32 MB 64 bit soDIMMs Small Outline Dual Inline Memory Modules After installing the memory modules the system automatically detects and reconfigures the total memory size during the POST routines The following lists important memory specifications Memory bus width 64 bit Expansion RAM module type 144 pin 64 bit small outline Dual Inline Memory Module soDIMM Expansion RAM module size...

Page 36: ... MB 0 MB 8 MB 0 MB 8 MB 8 MB 8 MB 8 MB 16 MB 16 MB 0 MB 16 MB 0 MB 16 MB 16 MB 16 MB 8 MB 24 MB 8 MB 16 MB 24 MB 16 MB 16 MB 32 MB 32 MB 0 MB 32 MB 0 MB 32 MB 32 MB 32 MB 8 MB 40 MB 8 MB 32 MB 40 MB 32 MB 16 MB 48 MB 16 MB 32 MB 48 MB 32 MB 32 MB 64 MB 1 4 9 Second Level Cache This notebook supports 256KB pipeline burst second level L2 cache ...

Page 37: ... 3 3V 5V type If 5V video chip is detected system maintains video voltage at 5V if 3 3V 5V video chip is detected system switches video voltage to 3 3V 1 4 11 1 External CRT Resolution Support Table 1 17 Supported External CRT Resolutions Resolution x Color on External CRT CRT Refresh Rate Simultaneous on TFT LCD Simultaneous on STN LCD CRT only Simultaneous SVGA SVGA 640x480x16 60 75 85 60 Y Y 64...

Page 38: ...256 Y Y 640x480x65 536 Y Y 640x480x16 777 216 Y 800x600x16 Y Y 800x600x256 Y Y 800x600x65 536 Y 1024x768x16 Y Y 1024x768x256 Y Y DSTN color number 256 colors TFT color number 65536 colors Maximum resolution LCD Panel 800x600 Maximum resolution External CRT 1280x1024 Using software you can set the LCD to a higher resolution than its physical resolution but the image shown on the LCD will pan ...

Page 39: ...n D type Location Rear side Selectable parallel port by BIOS Setup Parallel 1 3BCh IRQ7 Parallel 2 378h IRQ7 Parallel 3 278h IRQ5 Disable 1 4 13 Serial Port Table 1 20 Serial Port Configurations Item Specification Number of serial ports 1 16550 UART support Yes Connector type 9 pin D type Location Rear side Selectable serial port by BIOS Setup Serial 1 3F8h IRQ4 Serial 2 2F8h IRQ3 Disable ...

Page 40: ...ional Association The PCMCIA committee set out to standardize a way to add credit card size peripheral devices to a wide range of personal computers with as little effort as possible There are two type II I or one type III PC Card slots found on the left panel of the notebook These slots accept credit card sized cards that enhances the usability and expandability of the notebook ZV Zoomed Video po...

Page 41: ...901 0161R English Total number of keypads 84 85 keys Windows 95 keys Yes Logo key Application key Internal external keyboard work simultaneously Yes 1 4 17 1 Windows 95 Keys The keyboard has two keys that perform Windows 95 specific functions See Table 1 26 Table 1 25 Windows 95 Key Descriptions Key Description Windows logo key Start button Combinations with this key performs special functions Bel...

Page 42: ...ltage V 5 10 1 4 19 HDD Table 1 27 HDD Specifications Item Specification Vendor Model Name IBM DMCA21080 IBM DMCA21440 IBM DTNA22160 Toshiba MK1002MAV Drive Format Capacity MB 1080 1440 2160 1085 Bytes per sector 512 512 512 512 Logical heads 16 16 16 16 Logical sectors 63 63 63 63 Logical cylinders 2100 2800 4200 2100 Physical read write heads 3 4 6 6 Disks 2 2 3 3 Spindle speed RPM 4009 4009 400...

Page 43: ...rface Enhanced IDE ATAPI compatible Applicable disc format CD DA CD ROM CD ROM XA except ADPCM CD I Photo CD Multisession Video CD CD Loading mechanism Drawer type manual load release Power Requirement Input Voltage V 5 1 4 21 Battery Table 1 29 Battery Specifications Item Specification Battery gauge on screen Yes by hotkey Yes by hotkey Yes by hotkey Vendor model name Sanyo BTP W31 Sony BTP T31 T...

Page 44: ...in the battery charge level This prevents the battery from draining while the notebook is in use Table 1 30 Charger Specifications Item Specification Vendor model name Ambit T62 062 C 00 Input voltage from adapter V 19 min 20 typ 20 5 max Battery Low Voltage Battery Low 1 level V 10 7 typ for NiMH 8 65 typ for LIB Battery Low 2 level V 10 35 typ for NiMH 8 23 typ for LIB Battery Low 3 level V 9 22...

Page 45: ...0 7 9 1 4 24 DC AC Inverter DC AC inverter is used to generate very high AC voltage then supply to LCD CCFT backlight use and is also responsible for the control of LCD brightness Avoid touching the DC AC inverter area while the system unit is turned on Table 1 32 DC AC Inverter Specifications Item Specification Vendor model name Ambit T62 066 C 00 Ambit T62 064 C 00 Input voltage V 7 3 min 20 max...

Page 46: ... colors Optical Specification Contrast ratio 30 typ 30 typ 100 typ 100 typ Brightness cd m 2 70 typ 70 typ 70 typ 70 typ Brightness control keyboard hotkey keyboard hotkey keyboard hotkey keyboard hotkey Contrast control using keyboard hotkey using keyboard hotkey none none Electrical Specification Supply voltage for LCD display 3 3 or 5 typ 3 3 typ 3 3 3 3 typ 3 63 max Supply voltage for LCD back...

Page 47: ...fficiency of 83 minimum when measured at maximum load under 115V 60Hz Output Ratings CV mode DC output voltage V 19 Noise Ripple mV 300 Load A 0 min 2 4 max Dynamic Output Characteristics Turn on delay time s 115Vac 2 Hold up time ms 115 Vac input full load 5 min Over Voltage Protection OVP V 26 Short circuit protection Output can be shorted without damage Electrostatic discharge ESD kV 15 at air ...

Page 48: ... Display Toggle Switches display from LCD to CRT to both LCD and CRT Fn F4 Battery Gauge Displays the battery gauge Fn F5 Volume Control Press the scale hotkeys Fn and Fn to increase and decrease the output level Fn F6 Setup Gains access to BIOS Setup s Advanced System Configuration parameters Fn F7 Hibernation Standby Enters hibernation mode if the 0 volt suspend function is installed and enabled...

Page 49: ...System Introduction 1 31 1 5 1 3 Power Management Figure 1 14 Power Management Block Diagram ...

Page 50: ...ble 1 36 Standby Mode Conditions and Descriptions Condition Description The condition to enter Standby Mode Hard Disk Drive is Disabled in System Security of BIOS SETUP Hard Disk 0 is None in Basic System Configuration of BIOS SETUP HDD has not located enough free contiguous disk space generated by Sleep Manager and this free space is not corrupted Standby Hibernation Timer times out or Standby Hi...

Page 51: ...Battery low parameter in Setup If a battery low condition takes place the notebook enters hibernation mode in about five minutes Invoked by the operating system power saving modes When the notebook enters hibernation mode the whole system does not consume any power This is why hibernation mode is also called zero volt suspend To exit hibernation mode press the power switch When the PCMCIA I O card...

Page 52: ... the Display Standby Timer the display shuts off until you press a key or move the touchpad or external mouse Table 1 38 Display Standby Mode Conditions and Descriptions Condition Description The condition to enter Display Standby Mode Pointing device is idle until Display Standby Timer times out or LCD cover is closed The condition of Display Standby Mode All the system components are on except L...

Page 53: ... stays the same If you want a brighter picture you can then adjust the brightness and contrast level using hotkeys Fn F2 If you reconnect AC power to the system the system automatically adjusts the LCD backlight to its original level the brightness and contrast level before disconnecting the AC adapter If you adjusted the brightness and contrast level after disconnecting AC power the level stays t...

Page 54: ...t English Win95 PCMCIA To re install applications under Windows 95 click on Start then Run Based on the location of the application run the setup program to install the application The following table lists the applications and their locations Table 1 41 Location of Applications in the System Utility CD Name Function Location Sleep Manager 0V Suspend utility ENGLISH WIN95 SLEEPMGR Y Station Audio ...

Page 55: ...System Introduction 1 37 1 6 System Block Diagram Figure 1 15 System Block Diagram ...

Page 56: ...5G Sweep rate 1 minute octave Number of test cycles 2 axis X Y Z Non operating Vibration unpacked Non operating 5 27 1Hz 0 6G 27 1 50Hz 0 41mm 50 500Hz 2G Sweep rate 2 minutes octave Number of text cycles 4 axis X Y Z Shock Non operating unpacked 40G peak 11 1ms half sine Non operating packed 50G peak 11 1ms half sine Altitude Operating 10 000 feet Non operating 40 000 feet ESD Air discharge 8kV n...

Page 57: ...echanical Specifications Table 1 43 Mechanical Specifications Item Specification Weight FDD model CD ROM model includes battery 2 6 kg 5 7 lb 2 8 kg 6 2 lb Dimensions main footprint W x D x H 306mm x 228mm x 46mm 12 05 x 8 98 x 1 81 ...

Page 58: ...iption M1521 Acer System data buffer M1523 Acer System controller chip M7101 Acer Power management unit 65550 C T Chips Technology Video controller TI PCI1131 Texas Instrument PCMCIA controller NS87336VJG NS National Semiconductor Super I O controller YMF715 Yamaha Audio Chip T62 062 C Ambit Battery Charger T62 061 C Ambit DC DC Converter T62 064 C Ambit DC AC Inverter for 11 3 T62 066 C Ambit DC ...

Page 59: ...r to DRAM interface four PCI master arbiters and a UMA arbiter The M1521 bus interfaces are designed to interface with 3V and 5V buses It directly connects to 3V CPU bus 3V or 5V tag 3V or 5V DRAM bus and 5V PCI bus 2 2 1 Features Supports all Intel Cyrix AMD 586 class processors with host bus of 66 MHz 60 MHz and 50 MHz at 3V supports M1 K5 Dakota CPUs supports linear wrap mode for M1 Supports as...

Page 60: ...emory write posted buffers Convert back to back CPU to PCI memory write to PCI burst cycle DWORDS for PCI to DRAM write posted read prefetching buffers PCI to DRAM up to 133 MB sec bandwidth even when L1 L2 write back L1 L2 pipelined snoop ahead for PCI to DRAM cycle Supports PCI mechanism 1 only PCI spec 2 1 support N 16 8 8 rule passive release fair arbitration Enhanced performance for memory re...

Page 61: ...ce Guide 2 2 2 Block Diagram 586 CPU SRAM M1521 BGA DRAM HDD M1523 UMA Graphic controller IDE Master Aladdin III System Block Diagram CD CPU Bus PCI Bus ISA Bus USB connector Figure 2 1 Alladin III Block Diagram ...

Page 62: ...tem Architecture M1521 M1523 ALADDIN III SYSTEM ARCHITECTURE tag 8 11 bit TTL SRAM 208 PQFP RTC KBC 328 BGA 586 CPU addr data PCI ISA DRAM MD GC MA CTLR IDE bus HDD 128K 256K Flash XD TTL USB conn Figure 2 2 Alladin III System Architecture ...

Page 63: ...6 DWORD 5 DWORD 6 DWORD MUX PCI_OUT PCI_IN P_IN 31 0 PB_OUT 63 0 64 bit HDIN 63 0 MUX 72 bit ECC 72 bit SWAP 8 QWORD MUX MUX MUX MDIN 63 0 PCI_IN MD_IN 63 0 PB_IN 63 0 HD_IN SWAP H L DW swap for 32 bit DRAM MD_OUT M1521 MD_IN ECC partial W R path Figure 2 3 M1521 Data Path ...

Page 64: ...Major Chips Description 2 7 2 2 5 Pin Diagram Figure 2 4 M1521 Pin Diagram ...

Page 65: ...gnored by the M1521 ADSJ T5 I Address Strobe The CPU or M1521 starts a new cycle by asserting ADSJ first The M1521 does not precede to execute a cycle until it detects ADSJ active BRDYJ M5 O Burst Ready The assertion of BRDYJ means the current transaction is complete The CPU terminates the cycle by receiving 1 or 4 active BRDYJs depending on different types of cycles NAJ N5 O Next Address It is as...

Page 66: ...regardless of the state of KENJ KENJ INV K5 O Cache Enable Output This signal connects to the CPU s KENJ and INV pins KENJ is used to notify the CPU whether the address of the current transaction is cacheable INV is used during L1 snoop cycles The M1521 drives this signal high low during the EADSJ assertion of a PCI master write read snoop cycle SMIACTJ T10 I SMM Interrupt Active It is asserted by...

Page 67: ... cycle and a byte mask during a write cycle MA 11 2 V14 Y14 Y15 U14 W14 T13 U13 V13 W13 Y13 O DRAM Address lines These signals are the address lines of all DRAMs The M1521 supports DRAM types ranging from 256K to 64M MAA 1 0 T12 V12 O Memory Address copy A for 1 0 MAB 1 0 U12 W12 O Memory Address copy B for 1 0 MD 63 0 C15 A16 B17 A18 B19 B20 D19 E20 J19 K20 M18 N19 P20 R19 T18 V20 C14 D15 C16 D17...

Page 68: ...ress for 256 KB L2 caches TIO 6 0 contain the L2 tag address and TIO7 contains the L2 cache valid bit for 512 KB caches TWEJ V16 O Tag Write Enable This signal when asserted writes into the external tag new state and tag addresses PCI Interface AD 31 28 AD 27 24 AD 23 20 AD 19 16 AD 15 12 AD 11 08 AD 07 04 AD 03 00 A2 B2 A3 B3 A4 B4 C4 D6 B5 C5 A6 B6 C6 A7 B7 C7 C8 A9 B9 C9 A10 B10 C10 A11 C11 A12...

Page 69: ...ants PCI to M1523 PAR E12 I O Parity bit of PCI buses It is the even parity bit across PAD 31 0 and CBEJ 3 0 SERRJ E13 O System Error If the M1521 detects parity errors in DRAMs it asserts SERRJ to notify the system Clock Reset and Suspend Interfaces RSTJ T15 I System Reset This pin when asserted resets the M1521 and sets the register bits to their default values SUSPENDJ P6 I Suspend When activel...

Page 70: ...is output connects to the MGNTJ of the GUI device This pin can also be used as grant signal of the fifth PCI master PRIO G15 I Priority The high priority request from the GUI device Power Pins VCC F5 F6 G6 R6 R7 F14 F15 P15 R15 R16 P Vcc 3 3V VDD_5 E14 P Vcc 5 0V Vss or Gnd E15 T16 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 P Ground ...

Page 71: ...IDE devices providing an interface for IDE hard disks and CD ROMs The ATA bus pins are dedicated to improve the performance of IDE master The M1523 supports the Super Green feature for Intel and Intel compatible CPUs It implements programmable hardware events software event and external switches for suspend turbo ring in The M1523 provides CPU clock control STPCLKJ The STPCLKJ can be active low or...

Page 72: ... Play port support programmable chip select Steerable interrupt request lines PMU interface Supports CPU SMM mode SMI feature Supports programmable stop clock throttle Supports the APM control Provides external suspend mode switch turbo switch ring in switch Provides four system states for power saving on doze standby suspend Provides three timers from 1 second to 300 minutes to individually monit...

Page 73: ... PCICLK CBEJ 3 0 AD 31 0 FRAMEJ TRDYJ IRDYJ STOPJ DEVSELJ SERRJ PAR PHOLDJ PHLDAJ FERRJ IRQ 15 14 IRQ 11 3 INTAJ M1II NTBJ S0 INTCJ S1 INTDJ S2 IGNNEJ INTR NMI A20MJ USBCLK USBP 11 10 IDRQ 0 1 IDAKJ 0 1 IDERDY IDEIORJ IDEIOWJ IDESCS3J IDESCS1J IDEPCS3J IDEPCS1J IDE_A 2 0 IDE_D 15 0 SD 15 8 XD 7 0 SA 19 0 SBHEJ LA 23 17 IO16J M16J MEMRJ MEMWJ AEN IOCHRDYJ NOWSJ IOCHKJ SYSCLK BALE IORJ IOWJ SMEMRJ L...

Page 74: ...Q10 LA21 IRQ11 VDD BAT RTC32KII RTC32KI PWG LA20 LA19 IRQ15 LA18 IRQ14 LA17 MEMRJ DREQ0 Vss MEMWJ DACK5J SD8 DREQ5 SD9 DACK6J SD10 DREQ6 SD11 DACK7J SD12 DREQ7 SD13 VDD SD14 SD15 OSC14M SIRQI SIRQII USBCLK DACK0J DACK1J CPURST SMIJ STPCLKJ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 1...

Page 75: ...ndicate the beginning and duration of an access DEVSELJ 95 I O Device Select This indicates that the target device has decoded the address as its own cycle This pin is an output pin when the M1523 acts as a PCI slave that has decoded address as its own cycle including subtractive decoding IRDYJ 93 I O Initiator Ready indicates the initiator s ability to complete the current data phase of the trans...

Page 76: ...d by the internal 8259 NMI 58 O Non maskable Interrupt This is non maskable interrupt request to CPU A20MJ 56 O CPU A20 Mask This is the address line 20 mask signal ISA Interface FERRJ IRQ13 62 I Floating Point Error FERRJ input to generate IRQ13 When the coprocessor interface is disabled in configuration port 43h bit 6 the function of this pin is IRQ13 IRQ12 MDATAO 155 I O Mouse Interrupt Request...

Page 77: ...mory Device Indicator This signal indicates the memory device supports 16 bit transfers MEMRJ 24 I O ISA Memory Read This signal is an input during ISA master cycle MEMWJ 27 I O ISA Memory Write This signal is an input during ISA master cycle AEN 173 O ISA I O Address Enable Active high signal during DMA cycle to prevent I O device from misinterpreting the DMA cycle as valid I O cycle IOCHRDY 172 ...

Page 78: ...puts PCSJ O programmable chip select and DACKOJ O connected to external MUX chip enable TC 206 O DMA End of Process Hardware setting options Pulled low Support external I O APIC mode Pulled high Not support external I O APIC REFSHJ 191 I O ISA Refresh Cycle This signal is input during ISA master cycles but an output during other cycles Timer SPKR 43 O Speaker Output Hardware setting options Pulled...

Page 79: ...r SMM mode An external pull up should be placed on this signal if it is not used or it is not guaranteed to be always driven When external APIC mode is enabled this pin is APICREQJ SMIJ APICCSJ 50 O SMM Interrupt or APIC Chip Select A synchronous output asserted by the M1523 in response to one of many enabled hardware or software events When external APIC mode is enabled this pin is APICCSJ STPCLK...

Page 80: ...Pin Type Description IDE Interface IDE_D 15 0 135 132 130 128 126 124 122 119 121 123 125 127 129 131 133 136 I O IDE ATA Data Bus Vcc and Vss VCC3 53 P Vcc 3 3V VCC5 VBAT 14 P RTC Battery Input VCC5 40 72 105 120 156 208 P VCC 5 0V VDD Vss 1 26 52 82 104 134 157 182 P Vss or Ground ...

Page 81: ...rddisk Floppy Serial port Parallel port Keyboard Six programmable I O address groups activity monitor Two programmable memory address groups activity monitor Multiple external wake up events from DOZE or SLEEP to ON states External Push button Cover open Modem Ring RTC alarm DRQ Two level battery warning monitors 24 General Purpose I O pins Each pin can be programmed to become input or output 32 E...

Page 82: ...D14 AD13 AD12 AD11 AD10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GPIOC3 GPIOC2 GPIOC1 GPIOC0 GPIOA7 GPIOA6 GPIOA5 GPIOA4 GPIOA3 GPIOA2 GPIOA1 GPIOA0 Vss CLK32 SEL1 SEL0 VDD5 DISPLAY CCFT FPVEE SPKCTL SQWO SLED DRQ CRT 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ALi M7101 Figure 2 7 M7101 Pin Diagram ...

Page 83: ...mplete the current data phase of transaction TRDYJ 14 O Target Device Ready This signal indicates that M7101 is ready to complete the current data phase of transaction PAR 16 O Parity bit of PCI bus It is the even parity bit across AD 31 0 and CBEJ 3 0 CLK RESET interface 3 CLK32 62 I 32KHz clock This is 32KHz clock input used by internal timers and relative PMU circuit PWGD 40 I POWER GOOD When P...

Page 84: ...r both close and open will generate a doze to on or sleep to on SMIJ to wake the system up if the system is in Doze or Sleep state respectively Debounce circuit is built in It detects both rising and falling edge Suspend status 2 when 0F8h D7 0 it is default value It is suspend status 2 signal during 0 5V suspend system It will be low in normal When writing to port 0FAh it will go high to close th...

Page 85: ... signal FPVEE 56 I LCD backlight VEE LCD backlight VEE on off control signal Internal circuit uses this signal to generate DISPLAY and CCFT signals On one hand if FPVEE goes from low to high DISPLAY will go high after 62 5ms to 125ms If FPVEE goes low DISPLAY will go low immediately On the other hand FPVEE will AND with offset 0D2h D0 to generate CCFT That is if both FPVEE and offset 0D2h D0 are h...

Page 86: ... D7 0 D3 1 this signal will be asserted until reading writing all of SMIJ status register s bits or a programmed interval time out 3 If offset 0D2h D7 0 D3 0 this signal will be asserted for an interval time This can be treated as a pulse SMIJ SUSTATE 45 O SUSPEND STATE When writing to port 0FAh or POSSTA goes high the SUSTATE will go high The system will enter SUSPEND mode Only VDDS will supply t...

Page 87: ... PCI AD 23 16 if a byte command If a word command two 74245 will be used and4 outputs are connected to PCI AD 31 16 When read index 0E1h M7101 will send DEVSELJ TRDYJ but float the AD 31 0 because the data will be sent by 74245 The write action has no meaning and nothing will be done GPIOA3 CONTRAST2 SLOWDOW N 67 O O Contrast2 When offset 0F6h D14 0 and D9 1 this pin will be the LCD contrast outpu...

Page 88: ...0 GPIOB n input GPIOB n value can be read from Offset 0DAh D n 1 GPIOB n Output Offset 0DAh D n value will send to GPIOB n n value is from 7 to 0 GPIOB7 STPCLKJ 88 O Stop clock signal When DISPLAY is pulled low or offset 0F6h D14 1 this pin will become stop clock signal output It may be connected to CPU to force it into STPGNT or STPCLK mode Write port 0EFh will assert this function GPIOB6 AMSTATJ...

Page 89: ...I O attribute When programmed to be output offset 0DCh D 7 0 will set to corresponding signal When programmed to be input the signal can be read from the Offset 0DCh D 7 0 corresponding bits Offset 0DDh D n 0 GPIOC n input GPIOC n value can be read from Offset 0DCh D n 1 GPIOC n Output Offset 0DAh D n value will send to GPIOC n n value is from 7 to 0 GPIOC7 VCSJ 80 I VGA Chip select When offset 0F...

Page 90: ...ted Built in debounce circuit GPIOC 3 DOCKJ 75 Docking insert detected When index 0F6h D7 0 this signal is GPIOC 3 When it is 1 this signal will become DOCKJ When a rising falling edge happens at this input an SMIJ will be generated Built in debounce circuit GPIOC 2 BIOSA17 74 BIOS address ROM A17 When CCFT is low this signal will become BIOSA17 GPIOC 1 BIOSA16 73 BIOS address ROM A16 When CCFT is...

Page 91: ...finition When SLED default is pulled high the chip will be in normal mode When SLED is pulled low by 4 7K resistor the chip will be in test mode When GPIOC2 pull low the PCI ports are 0078 007A and offset 0F6h D15 will be set otherwise 0178 017A Table 2 5 M7101 Different Pin Definition Setting Original pin definition CCFT pull low 4 7K DISPLAY pull low 4 7K SPKCTL pull low 4 7K SQWO pull low 4 7K ...

Page 92: ... 6 M7101 Original Pin Definition Setting Original pin definition D6 1 D7 1 D8 1 D9 1 D10 1 D11 1 D12 1 D13 1 D14 1 GPIOA7 POSSTA GPIOA6 SPEKIN GPIOA3 CONTRAST2 SLOWDN GPIOA2 CONTRAST1 GPIOB7 STPCLKJ GPIOB3 BRDYJ GPIOC7 VCSJ GPIOC6 SETUP GPIOC5 EXTSW GPIOC4 EJECYJ GPIOC3 DOCKJ Following is the default pulled values of GPIOA GPIOB and GPIOC Pull high GPIOA0 GPIOA4 GPIOB1 GPIOB3 GPIOB6 GPIOB7 GPIOC1 ...

Page 93: ...20 AD15 I O 70 GPIOA6 I O 21 AD14 I O 71 GPIOA7 I O 22 AD13 I O 72 GPIOC0 I O 23 AD12 I O 73 GPIOC1 I O 24 AD11 I O 74 GPIOC2 I O 25 AD10 I O 75 GPIOC3 I O 26 VDD3 P 76 VDD5 P 27 AD9 I O 77 GPIOC4 I O 28 AD8 I O 78 GPIOC5 I O 29 CBEJ0 I 79 GPIOC6 I O 30 AD7 I O 80 GPIOC7 I O 31 AD6 I O 81 GPIOB0 I O 32 AD5 I O 82 GPIOB1 I O 33 AD4 I O 83 GPIOB2 I O 34 AD3 I O 84 GPIOB3 I O 35 AD2 I O 85 GPIOB6 I O...

Page 94: ...77 GPIOC4 I O 9 AD16 I O 78 GPIOC5 I O 8 AD17 I O 79 GPIOC6 I O 7 AD18 I O 80 GPIOC7 I O 6 AD19 I O 44 HOTKEYJ I 5 AD20 I O 13 IRDYJ I 4 AD21 I O 47 LBJ I 3 AD22 I O 48 LLBJ I 2 AD23 I O 16 PAR O 98 AD24 I O 89 PCICLK I 97 AD25 I O 50 PS2 I 96 AD26 I O 40 PWGD I 95 AD27 I O 42 RI I 94 AD28 I O 43 RTC I 93 AD29 I O 60 SEL0 I O 92 AD30 I O 61 SEL1 I O 91 AD31 I O 53 SLED O 29 CBEJ0 I 18 SMIJ O 17 CB...

Page 95: ...h address When it detects the address it will assert the DEVSELJ signal and TRDYJ when data is ready M7101 is only a PCI slave device no REQJ and GNTJ signal required All the PCI interface timing can meet the requirements of PCI spec V2 1 M7101 will monitor the PCI bus behavior to detect the Device access like HDD SIO PIO VGA memory range Floppy KBC and IO MEM group It will decode these addresses ...

Page 96: ...ilable except offset 0D1h Unlock Read available available Unlock Write available available State Machine for PCI Interface FRAMEJ 1 IDLE nocycle 1 when FRAMEJ 1 and IRDYJ 1 0 when others HIT 1 when read write port 178 17B 0 when others FRAMEJ 1 FRAMEJ 0 IRDYJ 0 IRDYJ 1 HIT 0 nocycle 0 and nocycle 0 and HIT 1 HIT 0 and FRAMEJ 1 nocycle 1 or FRAMEJ 0 BUS_BUSY TURN_AR OVER_S HITCMD3 HITCMD2 HITCMD 1 ...

Page 97: ...the screen The capture system can receive data from either the system bus or from the ZV enabled video port in either RGB or YUV format The input data can also scaled down before storage in display memory c g from any size larger than 320x240 down to 352x248 Capture of input data may also be double buffered for smoothing and to prevent image tearing The display system can independently place eithe...

Page 98: ...ular panel type LOW POWER CONSUMPTION The C T65550 employs a variety of advanced power management features to reduce power consumption of the display sub system and extend battery life Although optimized for 3 3V operation The C T65550 controller s internal logic memory interface bus interface and panel interfaces can he independently configured to operate at either 3 3V or 5V SOFTWARE COMPATIBILI...

Page 99: ...2 42 Service Guide 2 5 3 Pin Diagram Figure 2 10 C T 65550 Pin Diagram ...

Page 100: ...active 23 RDYRTN for 1x Clock config CRESET for 2x Clock config In Ready Return Handshaking signal in VL Bus interface indicating synchronization of RDY by the local bus master controller to the processor Upon receipt of this LCLK synchronous signal the chip will stop driving the bus if a read cycle was active and terminate the current cycle 24 LRDY Out OC Local Ready Driven low during VL Bus and ...

Page 101: ...A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 In In In In In In In In In In In In In In In In In In In In In In In In In In System Address Bus In VL Bus and direct CPU interfaces the address pins are connected directly to the bus In internal clock synthesizer test mode TS 0 at Reset A24 becomes VCLK out and A25 becomes MCLK out A26 and A27 may be alternately used as General Purpo...

Page 102: ...y to the processor data lines On the VL Bus they connect to the corresponding buffered or unbuffered data signal These pins are tri stated during Standby mode as are all other bus interface outputs PCI Bus Interface 207 RESET In Reset This input sets all signals and registers in the chip to a known state All outputs from the chip are tri stated or driven to an inactive state This pin is ignored du...

Page 103: ...s valid data is present on AD0 31 during a read it indicates the master is prepared to accept data A data phase is completed on any clock when both IRDY and TRDY are sampled then asserted wait cycles are inserted until this occurs 24 TRDY S TS Target Ready Indicates the target s ability to complete the current data phase of the transaction During a read TRDY indicates that valid data is present on...

Page 104: ...Out Out Out Out Out Out Out Out Out BlOS ROM Address Outputs See MAD8 15 pins 170 177 for BIOS ROM data inputs BIOS ROMs are not normally required in portable computer designs Graphics System BIOS code is normally included in the System BIOS ROM However the 65550 provides BIOS ROM interface capability for development systems and add in card Flat Panel Graphics Controllers Since the PCI Bus specifi...

Page 105: ...O I O I O I O I O PCI Address Data Bus Address and data are multiplexed on the same pins A bus transaction consists of an address phase followed by one or more data phases both read and write bursts are allowed by the bus definition The address phase is the clock cycle in which FRAME is asserted AD0 31 contain a 32 bit physical address For I O the address is a byte address for memory and configura...

Page 106: ...11 Memory Write Y 1000 reserved 1001 reserved 1010 Configuration Read Y 1011 Configuration Write Y 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Read Invalidate During the data phase these pins are byte enables that determine which byte lanes carry meaningful data byte 0 corresponds to AD0 7 byte 1 corresponds to 8 15 byte 2 corresponds to 16 23 byte 3 corresp...

Page 107: ...RAS for DRAM B or bank 1 in 2MB configurations 101 RASC VRDY KEY Out In RAS for DRAM C or color key input from external PC Video source or VAFC Video System Ready input 160 CASAL Out CAS for the DRAM A lower byte 159 CASAH Out CAS for the DRAM A upper byte 126 CASBL Out CAS for the DRAM B lower byte 125 CASBH Out CAS for the DRAM B upper byte 104 CASCL WECL VR6 VP14 I O DRAM C low byte CAS or vide...

Page 108: ...A Bus connector 127 128 129 130 131 132 133 134 135 136 137 138 140 141 143 144 MBD0 MBD1 MBD2 MBD3 MBD4 MBDS MBD6 MBD7 MBD8 MBD9 MBD10 MBD11 MBD12 MBD13 MBD14 MBD15 I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O Memory data bus for DRAM B upper 512KB 106 107 109 110 111 112 113 114 115 116 117 118 119 120 121 122 MCD0 VB2 EVID MCDI VB3 VP0 MCD2 VB4 VP1 MCD3 VB5 VP2 MCD4 VB6 VP3 M...

Page 109: ... configured as BLANK or as Display Enable DE for TFT Panels 62 61 ENAVDD ENAVEE ENABKL I O I O Power sequencing controls Power sequencing controls for panel driver electronics voltage VDD and panel LCD bias voltage VEE 53 ACTI I O Activity Indicator May be configured for other functions 54 ENBKL I O Enable Backlight Outputs May be configured for other functions Flat Panel Display Interface 65 HYSN...

Page 110: ...45 this pin formerly Crystal Out or XTLAO must be disconnected In addition pin 150 must be pulled down on reset The 65545 no longer supports the internal oscillator option 205 202 206 208 CVCC0 CGND0 CVCCI CGNDI VCC GND VCC GND Analog power and ground pins for noise isolation for the internal clock synthesizer Must be the same as VCC for internal logic VCC GND pair 0 and VCC GND pair 1 pins must b...

Page 111: ...3 UD7 B0 B0 B00 R1 R1 UR1 UR0 UR0 72 P1 UD2 UD6 B1 B1 B01 B1 G1 UG1 UG0 UG0 73 P2 UD1 UD5 B2 B2 B02 G2 B1 UB1 UB0 UB0 74 P3 UD0 UD4 B3 B3 B03 R3 R2 UR2 UR1 LR0 75 P4 LD3 UD3 B4 B4 B10 B3 G2 LR1 LR0 LG0 76 P5 LD2 UD2 G0 B5 B11 G4 B2 LG1 LG0 LB0 78 P6 LD1 UD1 G1 B6 B12 R5 R3 LB1 LB0 UR1 79 P7 LD0 UD0 G2 B7 B13 B5 G3 LR2 LR1 UG1 81 P8 P0 LD7 G3 G0 G00 SHFCLKU B3 UG1 UB1 82 P9 P1 LD6 G4 G1 G01 R4 UB1 ...

Page 112: ...DY RDY Tri Stated 25 LDEV Tri Stated 51 44 41 40 38 33 D0 15 Tri Stated 20 13 8 1 D16 31 Tri Stated S TS stands for Sustained Tri state These signals are driven by only one device at a time are driven high for one clock before released and are not driven for at least one cycle after being released by the previous device A pull up provided by the bus controller is used to maintain an inactive level...

Page 113: ...dows is also user by the PCI1131 to pass cycles between PCI and PC Card address spaces and host software must program the location and size of these windows when the PCI1131 or PC Card is initialized The PCI1131 also communicates via a three line serial protocol to he TI TPS2206 Dual PCMCIA Power Switch The TPS2206 switches Vcc and Vpp supply voltage to the two PC Card sockets independently Host s...

Page 114: ... register compatible with the Intel 82365SL DF ExCA controller The PCI1131 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent 32 bit write buffers allow fast posted writes to improve system bus utilization An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates...

Page 115: ...Available to each CardBus socket CardBus Memory Windows can be Individually selected prefetchable or non prefetchable ExCA Compatible Registers Are Mapped in Memory andfilO Space Texas Instruments TI Extension Registers Mapped in the PCI Configuration Space Intel 82365SL DF Register Compatible Supports 16 bit Distributed DMA on Both PC Card Sockets Supports PC PCI DMA on Both PC Card Supports ZOOM...

Page 116: ...Major Chips Description 2 59 2 6 4 Block Diagram Figure 2 11 Functional Block Diagram 16 bit PC Card Interface ...

Page 117: ...2 60 Service Guide Figure 2 12 Functional block diagram CardBus Card Interface ...

Page 118: ...Major Chips Description 2 61 2 6 5 Pin Diagram Figure 2 13 PCI to PC Card 16 bit terminal assignments ...

Page 119: ...2 62 Service Guide Figure 2 14 PCI to CardBus terminal assignments ...

Page 120: ...deasserting RSTIN the PCI1131 is in its default state When the 1131 SUSPEND mode is enabled the device is protected from any RSTIn reset i e the 1131 internal register contents are preserved PCI Address and Data Terminals AD31 170 AD30 171 AD29 173 AD28 174 AD27 176 AD26 177 AD25 178 AD24 179 AD23 183 AD22 184 AD21 185 AD20 186 AD19 188 AD18 189 AD17 190 AD16 191 AD15 204 AD14 205 AD13 206 AD12 20...

Page 121: ...sfers continue When FRAME is sampled high deasserted the transaction is in the final data phase GNT 168 I Grant Driven by the PCI arbiter to grant the PCI1131 access to the PCI bus after the current data transaction has completed IDSEL 182 I Initialization device select IDSEL selects the PCI1t31 during configuration accesses IDSEL can be connected to one of the upper 24 PCI address lines IRDY 195 ...

Page 122: ...equest 10 and 12 This terminal is software configurable and is used by the PCI 1131 to support the PCI Clock Run protocol When configured as CLKRUN by setting bit 0 in the System Control Register at offset 80h this terminal is an open drain output To select between IRQ10 and IRQ12 as the output use bit 7 of Register 80h TERMINAL Name Slot Slot I O TYPE FUNCTION A B 1 6 bit PC Card Address and Data...

Page 123: ...6 bit memory PC Cards that include batteries BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are kept high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and needs to be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost See the Card Status Change ...

Page 124: ... DMA operation REG 130 63 O Attribute Memory Select REG remains high for all common memory accesses When NES is asserted access is limited to attribute memory OE or WE active and to the l O space IORD or IOWR active Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information DMA Acknowledge This pi...

Page 125: ... DMA write operation WAIT 136 70 I Bus Cycle Wait WET is driven by a 16 bit PC Card to delay the completion of i e extend the memory or l O cycle that is in progress WE 110 46 O Write Enable WE is used to strobe memory write data into 16 bit Memory PC Cards VVE is also used for memory PC Cards that employ programmable memory technologies DMA Terminal Count This pin is used as TC during DMA operati...

Page 126: ...s PC Card Address and Data Signals Slots A and B CAD31 147 81 CAD30 145 79 CAD29 144 78 CAD28 142 77 CAD27 141 76 CAD26 133 67 CAD25 132 66 CAD24 131 65 CAD23 128 62 CAD22 126 60 CAD21 123 57 CAD19 121 55 CAD18 119 54 CAD17 118 53 CAD16 103 37 CAD15 101 35 CAD14 102 36 CAD13 99 33 CAD12 100 34 CAD11 98 32 CAD10 97 30 CAD9 95 29 CAD8 93 27 CAD7 92 26 CAD6 89 23 CAD5 90 24 CAD4 87 20 CAD3 88 21 CAD2...

Page 127: ... CardBus PC Card Interface System Signals Slots A and B CCLK 112 48 O CardBus PC Card Clock This signal provides synchronous timing for all transactions on the CardBus PC Card interface All signals except MST upon assertion CCLKRUN CIST CSTSCHG CAUDIO CCD2 1 and CVS2 1 are sampled on the rising edge of the clock and all timing parameters are defined with the rising edge of this signal The CardBus ...

Page 128: ...he PCI1131 is initiating the bus initiator ability to complete a current data phase of the transaction It is used in conjunction with CTRDY When both of these signals are sampled asserted a data phase is completed on any clock During a write CIRDY indicates that valid data is present on CAD31 0 and during a read it indicates the PCI 1131 as an initiator is prepared to accept the data Wait cycles a...

Page 129: ...e CSERR 136 70 I CardBus System Error This signal reports address parity error data errors on the Special Cycle command or any other system error where the result could be catastrophic such that the CardBus card may no longer operate correctly CSERR is open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error The assertion of this signal is synchronous t...

Page 130: ...one of the PC Cards When this pin is configured for IRQ9 it should be connected to the IRQ programmable interrupt controller IRQSER allows all IRQ signals to be serialized onto one pin This signal is configured in the Device Control Register of the TI Extension Registers IRQ11 PCDMAGNT 160 O Interrupt Request 11 This terminals software configurable and is used by the PCI 1131 to accept a grant for...

Page 131: ...rising edge of CLOCK The frequency of the clock is derived from dividing the PCICLK by 36 The maximum frequency of this signal is 2 MHz DATA 152 O Power Switch Data is used by the PCI1131 to serially communicate socket power control information Speaker Control Terminal SPKROUT SUSPEND 149 I O Speaker SPKROUT carries the digital audio signal from the PC Card SUSPEND when enabled this signal places ...

Page 132: ...naling protocol The parallel port is fully IEEE 1284 level 2 compatible The SPP Standard Parallel Port is fully compatible wit ISA and EISA parallel ports In addition to the SPP EPP Enhanced Parallel Port and ECP Extended Capabilities Port modes are supported by the parallel port A set of configuration registers are provided to control the Plug and Play and other various functions of the PC87336 T...

Page 133: ...DI baud rate support Infrared support on UART2 IrDA and Sharp compliant The Address Decoder 6 bit or 10 bit decoding External Chip Select capability when 10 bit decoding Full relocation capability No limitation Enhanced Power Management Special configuration registers for power down Enhanced programmable power down FDC command Auto power down and wake up modes 2 special pins for power management T...

Page 134: ...tion Registers UART 16550 or 16450 UART IrDA HP Sharp IR 16550 or 16450 General Purpose Registers Power Down Logic IEEEE1284 Parallel Port Hifh Current Driver Floppy Disk Controller with Digital Data Separator Enhabced 8477 I O Ports Control Interrupt Data Handshake Floppy Drive Interface OSC Interrupt and DMA Floppy Drive Interface Interrupt IR Interface Serial Interface Interrupt Serial Interfac...

Page 135: ...2 78 Service Guide 2 7 3 Pin Diagram Figure 2 16 NS87336VJG Pin Diagram ...

Page 136: ...r a 0 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 KΩ resistor AEN 18 I Address Enable When this input is high it disables function selection via A15 A0 Access during DMA transfer is not affected by this pin ASTRB 79 O EPP Address Strobe This signal is used in EPP mode as address strobe It is an active low signal BADDR0 BADDR1 72 71 I Base ...

Page 137: ... 10 17 I O Data These are bidirectional data lines to the microprocessor D0 is the LSB and D7 is the MSB These signals have a 24 mA sink buffered outputs DACK0 DACK1 DACK2 53 52 3 I DMA Acknowledge 0 1 2 These active low inputs acknowledge the DMA request and enable the RD and WR inputs during a DMA transfer It can be used by one of the following FDC or Parallel Port If none of them uses this inpu...

Page 138: ...h information to control four FDDs when bit 4 of the Function Enable Register FER is set DR0 exchanges logical drive values with DR1 when bit 4 of Function Control Register is set DR1 PPM Mode 83 O FDC Drive Select 1 This pin offers an additional Drive Select signal in PPM Mode when PNF 0 It is drive select 1 when bit 4 of FCR is 0 It is drive select 0 when bit 4 of FCR is 1 This signal is active ...

Page 139: ...ode as data strobe It is an active low signal DTR1 DTR2 69 61 O UARTs Data Terminal Ready When low this output indicates to the modem or data set that the UART is ready to establish a communications link The DTR signal can be set to an active low by programming bit 0 DTR of the Modem Control Register to a high level A Master Reset operation sets this signal to its inactive high state Loop mode ope...

Page 140: ...this pin follows the ACK signal input When it is noe enabled this signal is tri state This pin ia I O only when ECP is enabled and IRQ5 is configured IRQ6 Legacy Mode 95 O Interrupt 6 Active high output to signal the completion of the execution phase for certain FDC commands Also used to signal when a data transfer is ready during a non DMA operation IRQ7 Legacy Mode 94 I O Interrupt 7 Active high...

Page 141: ...le line for drive 0 when bit 4 of FCR 1 This signal is active low PD 43 O FDC Power Down This pin is PD output when bit 4 of PMC is 1 It is DR1 when bit 4 of PMC is 0 PD is active high whenever the FDC is in power down state either via bit 6 of the DSR or bit 3 of FER or bit 0 of PTR or via the mode command PD0 7 92 89 87 84 I O Parallel Port Data These bidirectional pins transfer data to and from...

Page 142: ...ed to one of the following output pins IRQ3 IRQ7 IRQ9 IRQ12 SIRQ12 and SIRQ13 can be also routed to IRQ15 Software configuration determines to which output pin the input pin is routed to SIRQ1 is multiplexed with IRQ15 SRIQ12 is multiplexed with DRATE1 MSEN1 CS0 and SIRQ3 is multiplexed with DRV2 PNF DR23 SLCT 80 I Parallel Port Select This input is set high by the printer when it is selected This...

Page 143: ...rite Data signal in PPM Mode when PNF 0 See PE WGATE Normal Mode 36 O FDC Write Gate This output signal enables the write circuitry of the selected disk drive WGATE has been designated to prevent glitches during power up and power down This prevents writing to the disk when power is cycled WGATE PPM Mode 80 O FDC Write Gate This pin gives an additional Write Gate signal in PPM mode when PNF 0 WP N...

Page 144: ...al power down and suspend resume that is indispensable with power conscious application 2 8 1 Features Built in OPL3 Supports Sound Blaster Game compatibility Supports Windows Sound System compatibility Supports Plug Play ISA 1 0a compatibility Full Duplex operation Built in MPU401 Compatible MIDI I O port Built in Joystick Built in the 3D enhanced controller including all the analog components Su...

Page 145: ...2 88 Service Guide 2 8 2 Pin Diagram Figure 2 17 YMF715 Block Diagram ...

Page 146: ...t mixed analog output OUTR 1 O Right mixed analog output VREFI 1 I Voltage reference input VREFO 1 O Voltage reference output AUXIL l I Left AUX1 input AUX1R l I Right AUX1 input AIJX2L l I Left AUX2 input AUX2R 1 I Right AUX2 input LINEL 1 I Left LINE input LINER 1 I Right LINE input MIC 1 I MIC input MIN 1 I Monaural input TRECL 1 Left Treble capacitor TRECR 1 Right Treble capacitor SBFLTL 1 Lef...

Page 147: ...hmitt 2rnA MIDI Data Receive TXD 1 O TTL 4mA MIDI Data Transfer VOLUP 1 I Schmitt 2mA Hardware Volume Up VOLDW l I Schmitt 2mA Hardware Volume Down X331 1 I CMOS 2mA 33 8688 MHz X33O 1 O CMOS 2mA 33 8688 MHz X24I 1 I CMOS 2mA 24 576 MHz X24O 1 O CMOS 2mA 24 576 MHz AVDD 2 Analog Power Supply put on 5 0V DVDD 3 Digital Power Supply put on 5 0 V or 3 3V AVSS 2 Analog GND DVSS 4 Digital GND Note I In...

Page 148: ...inning of charging battery will not be charged until its temperature within a certain interval and if start voltage is lower than another certain value the charger module provides trickle charge current to charge the battery which prevents fast charging could possibly damage the battery In addition maximum temperature protection and safe timer is provided during quick charge To maintain the capaci...

Page 149: ...ge Adapter 0V to 24V Output current 3A Total sink current of all O P pin output pin to DC DC not included 15mA Charge current 1 9A Operating temperature 0 to 60 Storage temperature 10 to 85 2 9 4 Electrical Characteristics Table 2 17 T62 062 C Electrical Characteristics Table Parameter Symbol Condition MIN TYP MAX UNITS INPUT External Adapter AC power Note 1 19 20 21 V Disable High Low Supply curr...

Page 150: ... Battery Low 1 High Low Supply Current BL1 I load 100uA 2 7 5 5 25 0 7 100 V V uA Battery Low 2 High Low Supply Current BL2 I load 100uA 2 7 5 5 25 0 7 100 V V uA BATTERY LOW VOLTAGE WARNING SIGNAL Battery Low 1 NiMH LIB 25 TC125PPM 10 53 8 50 10 70 8 65 10 86 8 80 V Battery Low 2 NiMH LIB 25 TC125PPM 10 19 8 08 10 35 8 23 10 50 8 38 V Battery Low 3 NiMH LIB 25 TC125PPM 9 07 7 58 9 22 7 73 9 36 7 ...

Page 151: ... Voltage limit 20V1V with maximum 24V over voltage as well as over current protection 2 9 5 Pin Diagram DC_BAT_OUT 1 o o 2 DC_BAT_OUT DC_BAT_OUT 3 o o 4 DC_BAT_OUT GND 5 o o 6 GND PERIPHERAL SYSTEM ON 7 o o 8 5VSB_OUT SYSTEM ON 9 o o 10 DISABLE BT_QCHG 11 o o 12 AD5V SMI 13 o o 14 S I U TH 15 o o 16 BL1 ID 17 o o18 BL2 GND 19 o o20 BAT_IN_USE BT_VS 21 o o22 GND BT 23 o o24 BT BT 25 o o26 BT Figure...

Page 152: ...s when quick charge output logic high 12 AD5V O P when adapter inserted output 5V 10mA max 13 SMI O P open collector when push power on switch then output low delay 6040 mS 14 S I U I P logic high when system in use power 15 TH I P connecting to thermistor inside battery pack using 103AT 2 10K 25 1 16 BL1 O P when battery voltage lower than BL1 voltage then output low available when S I U 17 ID I ...

Page 153: ... precharge or quick charge is on B FOR LIB BATTERY When the charger module charges a 9 cells 3 s parallel 3 s serial LIB battery The charger will offer 1 90 1A charger current when system not in use power whereas 0 650 07A when system in use power Quick charge will be terminated when charge current less then 150mA60mA Then 12 67V 0 05V constant voltage with one hour timer will be applied to charge...

Page 154: ...e are within the configured ranges If the voltage is less than the low voltage threshold the charger module provides trickle current to charge the battery This prevents fast charging could possibly damage the battery Also when the temperature of battery pack is over the temperature threshold the charger module will not charge the battery until its temperature within a configured range This prevent...

Page 155: ... for 3 cells Lithium Ion or 10 cells NiMH battery input Pentium based Notebook PC The converter also supplies P G signal 2 35V 2 45V 2 9V 3 1V switch for CPU and ON OFF control 2 10 1 Pin Diagram Figure 2 19 T62 061 C Pin Diagram 2 10 2 Pin Assignment Table 2 19 T62 061 C Pin Descriptions Pin No Description 1 2 GND 3 DC IN 4 P G Vcc 5 5 0V 6 GND 7 6V 8 12V 9 GND 10 3 3V 11 5VSB 12 ON OFF 13 P G 14...

Page 156: ... 100mV max OVP 6 5 8 2V Short circuit protection Fuse protection Ripple max 75mV when regulate in IDLE mode 3 3V Load 0A 3 3A Regulation 5 5 Ripple 50mV max Noise 100mV max OVP 4 5 6 2V Short circuit protection Fuse protection Ripple max 75mV when regulate in IDLE mode 2 9V 3 1V Load 0A 3 0A Regulation 5 4 Ripple 50mA max Noise 100mV max OVP 3 3 5 0V Short circuit protection Fuse protection Ripple...

Page 157: ... 5A 5VSB Load 5mA Regulation 10 Ripple 75mV max Noise 250mV max P G Active high within 100ms to 500ms after system s 5V 3 3V and Vcpu are all in regulation Driving capability 12uA source 200uA sink 2 10 4 Control VCPU Control Control switch can switch Vcpu output voltage to 2 35V2 45V2 9 or 3 1V ON OFF A logic low will turn off 5V 3 3V 2 35V 2 45V 2 9V 3 1V 12V and 6V main o p The DC DC converter ...

Page 158: ... The recommended value is 30uF Amps TAN or OS CON CAP Efficiency 90 MIN at 12V input and 5V 1 5A 3 3V 0 8A 2 9V 0 6A load Environment Operating Temperature 0 to 65 Relative Humidity 10 to 95 Shipping Storage Temperature 25 to 85 Relative Humidity 10 to 95 ...

Page 159: ...ions Electrical Characteristics Table 2 21 Electrical Characteristics ITEM SYMBOL MIN TYP MAX UNIT REMARK INPUT VOLTAGE Vin 7 0 22 0 V INPUT CURRENT Iin 600 mA NO LOAD VOLATAGE Vs 1400 Vrms WORKING FREQUENCY f 45 60 KHz TUBE CURRENT OUTPUT MAX Iout 5 5 6 0 6 5 mArms PWM 100 TUBE CURRENT OUTPUT MIN Iout 0 5 1 0 1 5 mArms PWM 25 CONTRAST VOLTAGE OUTPUT MAX VEE 2 15 2 3 2 45 Vrms PWM 100 CONTRAST VOL...

Page 160: ...iption PIN NO SYMBOL DESCRIPRION 1 DCBATTIN DC 7 0V 21 0V 2 GND POWER GND 3 CCFTON PWM SIGNAL FOR ON OFF AND BRIGHTNESS CONTROL 4 DATA ID X24C02 DATA 5 5 0V 5 0V 10 6 SGND LOGIC GND FOR X24C02 7 N C 8 CK CLOCK FOR X24C02 9 N C 10 VEE VEE OUTPUT 11 CTEN CONTRAST ON OFF TTL LEVEL H ON 12 CTVREN PWM SIGNAL FOR CONTRAST VOLTAGE J2 SM02 8 0 B BHS 1 TB2P JST Table 2 23 Pin Description PIN NO SYMBOL DESC...

Page 161: ...2 104 Service Guide 2 11 3 Top Overlay Figure 2 20 T62 064 C DC AC Inverter Top Overlay diagram 2 11 4 Bottom Overlay Figure 2 21 T62 064 C DC AC Inverter Bottom Overlay diagram ...

Page 162: ...cal Characteristics Table 2 24 Electrical Characteristics ITEM SYMBOL MIN TYP MAX UNIT REMARK INPUT VOLTAGE Vin 7 0 21 0 V INPUT CURRENT Iin 650 mA NO LOAD VOLATAGE Vs 1400 Vrms WORKING FREQUENCY f 45 60 KHz TUBE CURRENT OUTPUT MAX Iout 5 5 6 0 6 5 mArms PWM 100 TUBE CURRENT OUTPUT MIN Iout 0 5 1 0 1 5 mArms PWM 25 Tc 25 Vin 7 0V TO 21 0V Operation Conditions OPERATING TEMPERATURE 0 TO 50 OPERATIN...

Page 163: ... SIGNAL FOR ON OFF AND BRIGHTNESS CONTROL 4 DATA ID X24C02 DATA 5 5 0V 5 0V 10 6 SGND LOGIC GND FOR X24C02 7 N C 8 CK CLOCK FOR X24C02 9 N C 10 VEE VEE OUTPUT 11 CTEN CONTRAST ON OFF TTL LEVEL H ON 12 CTVREN PWM SIGNAL FOR CONTRAST VOLTAGE J2 SM02 8 0 B BHS 1 TB2P JST Table 2 26 J2 SM02 8 0 B BHS 1 TB2P JST Pin Description PIN NO SYMBOL DESCRIPRION 1 VOUT1 Lanp Input HV 2 NC 3 VOUT2 Lanp Input LV ...

Page 164: ...Major Chips Description 2 107 2 12 3 Top Overlay Figure 2 22 T62 066 C DC AC Inverter Top Overlay diagram 2 12 4 Bottom Overlay Figure 2 23 T62 066 C DC AC Inverter Bottom Overlay diagram ...

Page 165: ...manager See section 5 3 for details 3 1 When to Use Setup The notebook is already correctly configured for you and you do not need to run Setup If you make any changes to the notebook or you receive an Equipment Configuration Error message after you turn on the notebook you need to run Setup Run Setup also if you want to do any of the following Change the system date time or speed Add or remove se...

Page 166: ...igating the Setup screens SETUP SCREEN NOTES From the main menu press or to move from one menu item to another and press Enter to enter the selected menu When accessing multi page sections press PgDn and PgUp to go through the pages Parameters displayed in low brightness grayed out are not user configurable The notebook detects and sets the values for these parameters Press or to move from one par...

Page 167: ... you press Esc to exit the Setup utility the following prompt appears Do you want to save CMOS data Yes No Select Yes to save the changes you made to the configuration values or No to abandon the changes and retain the current values ...

Page 168: ...is setting applies to both an internal and external floppy drive configuration Diskette Drive B by default is set to None Enable this parameter if two floppy drives are connected to the notebook 3 3 3 Hard Disk Drive The default setting for IDE Drive 0 is Auto With this setting the BIOS automatically detects your drive parameters You can also opt to key in your drive parameters by setting this par...

Page 169: ...ses on boot up Table 3 1 describes the different settings If notebook resolution is set at 640x480 the image on the notebook and external monitor will not be full screen For full screen image set up notebook at 800x600 resolution Table 3 1 Display Device Settings Setting Description Auto default If an external display is present the notebook uses the external display otherwise the LCD is the displ...

Page 170: ...ailable options Table 3 2 Floppy Disk Drive Control Settings Setting Description Normal default Floppy drive functions normally Write Protect Boot Sector Disables the floppy drive write function on a diskette s boot sector This option is for operating systems that access the floppy drive 100 percent via BIOS only Disabled Disables the floppy drive 3 4 2 Hard Disk Drive Control This parameter allow...

Page 171: ... boots from hard disk C If hard disk C is not a system disk an error message appears Drive A Notebook boots from floppy drive A If no diskette is present or if the diskette in floppy drive A is a non system disk an error message appears An installed PCMCIA bootable card overrides the System Boot Drive setting The notebook supports SRAM card boot 3 4 4 CD ROM Bootable When enabled the notebook chec...

Page 172: ...rameter are 278h IRQ 5 3BCh IRQ 7 Disabled 3 4 7 Parallel Port Operation Mode The parallel port supports four operation modes Standard and Bidirectional Extended Capabilities Port ECP Standard and Unidirectional Enhanced Parallel Port EPP ECP or Extended Capabilities Port supports a 16 byte FIFO first in first out which can be accessed by host DMA cycles and PIO cycles ECP boosts I O bandwidth to ...

Page 173: ...f up to seven characters which do not appear on the screen when you type them After typing your password press Enter Another prompt appears asking you to retype your password to verify your first entry After setting a password the notebook sets this parameter to Enabled The next time you boot the notebook resume from hibernation mode or run the Setup utility the password prompt appears Key in the ...

Page 174: ... not needed and set to Disabled If in case you install an older version of Windows 95 which does not have built in Cardbus driver support you need to enable this parameter The default setting is Disabled To verify your Windows 95 version access the System icon in the Control Panel In the System section of the General tab verify that the Windows 95 version is 4 00 950 B ...

Page 175: ...bled by the user Select Disabled to turn off all the timers The default setting is Enabled You cannot disable this parameter in Setup if APM is installed under DOS Windows or Windows 95 To disable APM type Power Off under DOS or disable the Power icon in the Windows Control Panel 3 5 2 Display Standby Timer The notebook shuts off the LCD backlight and turns off the CRT video as well if there is no...

Page 176: ...abled the notebook resumes from standby mode at the specified Resume Date and Resume Time parameter settings When the notebook is in hibernation mode it cannot resume when this parameter is enabled 3 5 7 System Resume Date and Time The Resume Date and Resume Time parameters let you set the date and time for the resume operation The date and time fields take the same format as the System Date and T...

Page 177: ... or disable the warning beep generated by the notebook when a battery low condition occurs The default setting is Enabled 3 5 10 Sleep Upon Battery low This parameter enables the notebook to enter standby or hibernation mode when a battery low condition takes place The default setting is Enabled ...

Page 178: ...d CPU Clock 133 MHz External Cache 256KB Enabled System DRAM 16 MB Pointing Device Detected Video DRAM 1 MB Internal KB 85 key Floppy Disk A 1 44 MB Security Normal Floppy Disk B None Security Normal Hard Disk 1160 MB Security Normal CD ROM None System Boot Drive Drive A Then Drive C CD ROM Bootable Disabled Serial Port 1 3F8h IRQ4 Parallel Port 378h IRQ7 Operation Mode Standard and Bidirectional ...

Page 179: ...ty Shows hard disk drive security setting CD ROM Shows the presence of a CD ROM drive System Boot Drive Shows the boot sequence setting CD ROM Bootable Shows if the CD ROM Bootable feature is enabled or not Serial Port 1 Shows the serial port base address and IRQ Parallel Port Shows the parallel port base address and IRQ Operation Mode Shows the parallel port operation mode Internal Cache Shows th...

Page 180: ...ues initially stored in CMOS RAM intended to provide high performance If in the future you change these settings you can load the default settings again by selecting this option When you select this option the following prompt appears Load Setup Default Settings Are you sure Yes No Select Yes to load the default settings or No to abort the operation ...

Page 181: ...shooting To disassemble the computer you need the following tools Wrist grounding strap and conductive mat for preventing electrostatic discharge Flat bladed screwdriver Phillips screwdriver Hexagonal screwdriver Tweezers Plastic stick The screws for the different components vary in size During the disassembly process group the screws with the corresponding components to avoid mismatch when puttin...

Page 182: ...l peripherals 2 Unplug the AC adapter and all power and signal cables from the system 3 Remove the battery pack from the notebook by 1 pressing the battery compartment cover release button and sliding out the cover Then 2 pull out the battery pack Figure 4 1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process ...

Page 183: ...nectors before pulling out the cables Do not force cables out of the connectors CONNECTORS WITH LOCKS Unplugging the Cable To unplug the cable first unlock the connector by pulling up the two clasps on both sides of the connector with a plastic stick Then carefully pull out the cable from the connector Plugging the Cable To plug the cable back first make sure that the connector is unlocked then pl...

Page 184: ...ble the inside assembly frame in that order Table 4 1 Guide to Disassembly Sequence Service Item Prerequisite Remove or replace the hard disk drive 1 Remove HDD Door Remove or replace the internal module 1 Remove the keyboard 2 Disassemble the housing Remove the motherboard for service or replacement 1 Remove the keyboard 2 Disassemble the housing Remove the touchpad 1 Remove the keyboard 2 Disass...

Page 185: ...Disassembly and Unit Replacement 4 5 Figure 4 3 Disassembly Sequence Flowchart ...

Page 186: ...e Memory Door 3 Remove the memory modules from its shipping container 4 Align the connector edge of the memory module with the key in the connector Insert the edge of the memory module board into the connector Use a rocking motion to fully insert the module Push downward on each side of the memory module until it snaps in place To remove the memory module release the slot locks found on both ends ...

Page 187: ... using an operating system other than Windows 95 or DOS you may need to re partition your hard disk drive to allow for the additional memory Check with your system administrator 4 3 Removing the Hard Disk Drive Follow these steps to remove the hard disk drive 1 Turn the computer over and locate the hard disk drive bay cover 2 Remove the screw that secures the hard disk drive bay cover Then slide o...

Page 188: ...ndle Be careful pulling the hard disk drive out Make sure the connector of the hard disk drive transfer board doesn t loosen while removing the hard disk drive Figure 4 7 Removing the Hard Disk Drive 4 Store the hard disk drive in an antistatic bag If you want to install a new hard disk drive reverse the steps described above ...

Page 189: ...the keyboard 1 Slide out 1 and pull up 2 the two display hinge covers on both sides of the notebook Figure 4 8 Removing the Display Hinge Covers 2 Unplug the keyboard connectors CN1 and CN2 from the keyboard connection board Set aside the keyboard Figure 4 9 Unplugging the Keyboard Connectors ...

Page 190: ... and during its course includes removing and replacing of certain major components like the internal drive CD ROM or floppy CPU and the main board Follow these steps 4 5 1 Removing the Heat Sink Assembly Remove the four screws that secure the heat sink to the housing Figure 4 10 Removing the Heat Sink Assembly Screws ...

Page 191: ...e FDD CD module latches 2 Unplug the internal drive cable CN14 CN17 for CD ROM or CN14 for FDD 3 Pull out the internal drive and set it aside Ensure the drive cables do not become hooked on the inside frame assembly when removing and reinstalling the drive Figure 4 11 Removing the Internal Drive ...

Page 192: ...ade screwdriver into the opening at the left end of the socket labeled OPEN and push towards the other end of the socket 2 Pull out the CPU Then insert the replacement CPU Insure the CPU is properly keyed before pressing it into the socket 3 Insert a flat blade screwdriver into the opening at the right end of the socket labeled LOCK and push towards the other end of the socket Old CPU New CPU Figu...

Page 193: ...the two screws that secure the display cable to the motherboard Then unplug the display cable Figure 4 13 Unplugging the Display Cable 2 Remove the four display hinge screws Then detach the display from the main unit and set aside Figure 4 14 Removing the Display Hinge Screws ...

Page 194: ...not need to remove all six screws Follow the discussion below for details If you only want to remove the top cover from the lower case remove all screws except for the encircled ones in this figure below If you intend to remove the motherboard with the chasis from the lower case remove all screws Figure 4 15 Removing the Bottom Screws ...

Page 195: ...isplay hinge screw holes and one screw near the PC card slots Before you detached the top cover make sure that you unplug the cable for the CN19 touch pad Unsnap the top cover from the base assembly and set aside Figure 4 16 Detaching the Top Cover from the Base Assembly ...

Page 196: ...uide 4 5 6 Removing the Base Assembly Remove four screws that secure the inside frame assembly to the base assembly Then detach the inside frame assembly from the base assembly Figure 4 17 Detaching the Base Assembly ...

Page 197: ...d 4 unplugging the fan cable CN9 Figure 4 18 Removing the Fan When installing the fan the fan hole should face the rear of the unit to draw thermal air out of the system 2 Remove the audio board by 1 unplugging the audio board connector CN5 and then 2 pulling up the audio board Figure 4 19 Removing the Audio Board ...

Page 198: ...attery connector board cable CN18 Figure 4 20 Removing the Battery Connector Board 4 Unplug the a LCD cover switch cable CN8 and b speaker cables CN7 and CN10 Figure 4 21 Unplugging the LCD Cover Switch and Speaker Cables CN7 CN8 CN10 ...

Page 199: ...de of the assembly frame Then remove the board Figure 4 22 Removing the Charger Board 6 Remove seven screws that secure the motherboard to the inside assembly frame Then release the latch and pull up the motherboard to detach it from the inside assembly frame Figure 4 23 Detaching the Motherboard from the Inside Assembly Frame ...

Page 200: ...onnector Module is normally part of the motherboard spare part The following removal procedure is for reference only Figure 4 24 Removing the PC Card Slot Unit REMOVING THE KEYBOARD CONNECTION BOARD Pull up the keyboard connection board to remove it Figure 4 25 Removing the Keyboard Connection Board ...

Page 201: ...hpad assembly 1 Peel off the mylar 2 Remove the three screws and disconnect the touchpad cable J2 then remove the touchpad main sensor and connector unit 3 Lift up and remove the touchpad 4 Lift up and remove the touchpad buttons Figure 4 26 Removing the Touchpad Touchpad mylar Touchpad cable Touchpad and circuit Touchpad knob Screw list x 3 M2L4 ...

Page 202: ...g bumper on the LCD hinge Figure 4 27 Removing the LCD Bumpers 2 Remove five screws on the display bezel or Screw List x4 M2 5L6 x1 M2 5L6 for TFT LCD x1 M2 5x8 for STN LCD Figure 4 28 Removing the Display Bezel Screws STN and TFT LCDs use the same bezel but different panels Screw List x4 M2 5L6 x1 M2 5L6 for 11 3 TFT LCD x1 M2 5x8 for 11 3 STN and 12 1 TFT LCD ...

Page 203: ...inside of the bezel sides and lower bezel area Then pull up the top bezel area 3 1 1 1 2 2 Figure 4 29 Removing the Display Bezel 4 Twist 1 then slide out 2 and remove the Hinge Cable Cover Figure 4 30 Removing the Hinge Cable Cover The hinge cable cover cannot be removed unless the LCD bezel is removed ...

Page 204: ...ck the foil around the display panel and unplug the inverter cable J2 The encircled screw doesn t exist in STN LCD model Figure 4 31 Removing the LCD Panel 6 Tilt the LCD Panel away for the display cover Then unplug the LCD Panel from the Display Cable Assembly Figure 4 32 Removing the LCD 1 2 ...

Page 205: ...cover and remove the inverter boards Then unplug the display cable Figure 4 33 Removing the DC AC Inverter and LCD ID Inverter Boards 5 Remove five screws that secure the LCD cable to the display back over then remove the LCD cable assembly Screw list x1 M2L4 x4 M2 5L5 Figure 4 34 Removing the Display Cable Assembly ...

Page 206: ...FDD 8MB 9 Intel 120mhz CPU NiMH BTY FDD 16MB A Intel 120mhz CPU NiMH BTY FDD 8MB Generic B Intel 133MHz CPU NiMH BTY FDD 8MB C Intel 133MHz CPU NiMH BTY FDD 16MB D Intel 133MHz CPU NiMH BTY FDD 16MB Generic E W O CPU Li Ion BTY CD ROM bulk pack F W O CPU NiMH BTY CD ROM bulk pack G W O CPU NiMH BTY FDD bulk pack H W O CPU Li Ion BTY FDD bulk pack I W O CPU W O BTY 0MB RAM bulk pack J Intel P55C 13...

Page 207: ...A 2 Service Guide 370PXX X X X Hard Disk 0 No Hard Disk 3 340MB A 1GB 1 120MB 5 520MB C 1 35GB 2 200MB 8 810MB D 1 4GB B 250MB 9 1 3GB E 2 1GB LCD C 11 3 DSTN CX 11 3 TFT DX 12 1 TFT ...

Page 208: ...A p p e n d i x B A p p e n d i x B Exploded View Diagram Exploded View Diagram B 1 This appendix shows an exploded view diagram of the notebook ...

Page 209: ...B 2 Service Guide ...

Page 210: ...Exploded View Diagram B 3 ...

Page 211: ...A 14 56 02568 031 9815585 0001 10 HDD 2160MB IBM DTNA 22160 56 02941 011 9815586 0001 11 HDD TRANSFER BD 55 48403 001 9811802 0001 w connector 12 ASSY HDD UPPER COVER 60 48412 101 9811783 0001 44 w mylar 13 ASSY HDD LOWER COVER 60 48418 101 9811785 0001 46 w mylar belt sponge 14 TOUCHPAD SYNAP TM1202MPU 156 1 56 17450 011 9811777 0001 22 w o label 15 ASSY HINGE COVER CAP R 050 AN370 60 46906 001 9...

Page 212: ...diaper assy latch hinge R no TI logo 2 ASSY C A 31P FPC 11 3 STN 370 6M 48412 001 9811791 0001 1 2 w tail diaper 3 LCD PANEL LCDM sanyo 11 3 DSTN 56 07469 001 9815588 0001 4 ASSY LCD BEZEL 11 3 050 370P 60 46902 101 9811793 0001 14 W LENS 5 INVERTER BD 19 21030 101 9811790 0001 12 LCD KIT TFT LG 12 1 1 COVER ASSY LCD PNL 60 48401 171 9815589 0001 1 w lens diaper assy latch hinge R no TI logo 2 ASS...

Page 213: ...LOGO PLATE EXT 610CD 40 46813 051 9811820 0001 12 LOGO PLATE EXT 610CDT 40 46813 061 9811821 0001 13 LOGO PLATE EXT 616 40 46813 101 9815703 0001 14 CLOSE COVER SWITCH W A 2P 50MM W CVR SW EXT 61X 50 46911 021 9811822 0001 15 KNOB TH MOUSE BUTTONS 42 46912 001 9811823 0001 23 16 COVER SIMM MEMORY EXT 61X 34 46904 001 9815575 0001 87 17 CABLE ASSY TOUCHPAD FPC EXT 61X 50 48401 001 9815577 0001 18 H...

Page 214: ... Keyboard Sws Ger 90 46907 007 9805758 0006 27 w cable Keyboard Italian 90 46907 00I 9805758 0007 27 w cable Keyboard Portuguese 90 46907 00P 9805758 0008 27 w cable Keyboard Sweden 90 46907 00W 9805758 0010 27 w cable Keyboard Denmark 90 46907 00D 9805758 0012 27 w cable Keyboard Norwegian 90 46907 00N 9805758 0013 27 w cable Keyboard Finland 90 46907 008 9805758 0014 27 w cable Keyboard Belgium ...

Page 215: ...AL22 5R0 10 PCS see above kit 3 M2L14 86 1A522 140 10 PCS see above kit 4 M2 5L5 86 4A553 5R0 10 PCS see above kit 5 M2 5L6 BLACK 86 1AI23 6R0 10 PCS see above kit 6 M2 5L6 86 1A553 6R0 10 PCS see above kit 7 M2 5L8 86 1A553 8R0 10 PCS see above kit 8 M2 5L18 86 1A523 180 10 PCS see above kit 9 M3L6 86 4A524 6R0 10 PCS see above kit MYLAR PACK 6M 48420 001 9815701 0001 1 MYLAR TH 40 46911 001 see ...

Page 216: ...001 FILE TRANSFER CABLE 50 30014 001 50 30014 001 9811767 0001 Power AC ADAPTER ASSY EXTENSA 61X w power cord 91 48428 011 9811754 0001 BATTERY PACK EXTENSA 61X NIMH SANYO 91 46928 012 9811738 0001 BATTERY PACK EXTENSA 61X NIMH TOSHIBA 91 46928 007 9811738 0003 LI ION 91 46928 003 370 370P EXT61X 91 46928 003 9811763 0001 Memory 8 MB memory modules 91 46910 001 9811344 0001 16 MB memory modules 91...

Page 217: ...A p p e n d i x D A p p e n d i x D Schematics This appendix shows the schematic diagrams of the notebook ...

Page 218: ... 7 1 V C C 2 A N 1 3 2 7 3 V C C 2 A N 1 5 2 7 5 V C C 2 A N 1 7 2 7 7 V C C 2 A N 1 9 2 7 9 V C C 2 A 7 7 D27 C21 58 D15 A35 35 D28 D22 59 D29 C19 56 D30 D20 57 D31 C17 54 P 2 G N D 1 1 9 A F 2 G N D 1 9 9 N C A 3 3 N C W 3 5 1 6 5 N C R 3 4 1 3 4 N C B 2 2 N C W 3 3 1 6 3 V C C 3 A N 2 5 2 8 5 V C C 3 A N 2 7 2 8 7 V C C 3 A N 2 9 2 8 9 B 2 6 G N D 2 6 B 2 8 G N D 2 8 H 2 G N D 8 9 H 3 6 G N D 9...

Page 219: ... O L D 1 5 9 K E N J I N V 1 4 9 C A C H E J 1 3 9 M I O J 1 2 9 H L O C K J 1 1 8 D C J 2 1 5 H I T M J 2 1 6 W R J 2 1 7 S M I A C T J 2 1 8 TIO10 MWEJ1 308 TIO9 SRASJ1 307 TIO8 SCASJ1 287 TIO7 306 TIO6 286 TIO5 266 TIO4 222 TIO3 265 TIO2 245 TIO1 244 TIO0 191 C A D V J C A A 4 J 2 6 3 C A D S J C A A 3 J 2 8 3 C C S J 2 8 4 G W E J 3 0 4 C O E J 2 4 3 B W E J C G C S J 3 0 5 T W E J 2 6 4 H C L...

Page 220: ... 28 CBEJ2 8 CBEJ3 5 F R A M E J 8 6 D E V S E L J 8 9 I R D Y J 8 7 T R D Y J 8 8 S T O P J 9 1 L O C K J 8 5 R E Q J 3 7 3 R E Q J 2 7 1 R E Q J 1 6 9 R E Q J 0 6 7 G N T J 3 7 4 G N T J 2 7 2 G N T J 1 7 0 G N T J 0 6 8 P H O L D J 6 4 P H L D A J 6 5 P A R 9 2 S E R R J 9 3 R S T J 2 2 3 M R E Q J 3 2 7 M G N T J 3 2 5 P R I O 3 2 6 P C L K I N 9 0 32K 285 3 V 1 0 5 3 V 1 0 6 3 V 1 1 9 3 V 2 0 ...

Page 221: ...L K 1 8 3 R T C R O M C S J 1 5 8 B A L E 2 S B H E J 6 M 1 6 J 7 I O 1 6 J 9 K B I N H I R Q 1 1 5 1 K B C L K K B C S J 1 5 2 K B D A T A 1 5 3 M S C L K 1 5 4 S I R Q I 4 4 S I R Q I I I R Q 8 J 4 5 R T C 3 2 K O 1 5 R T C 3 2 K I 1 6 C P U R S T 4 9 S M I J A P I C C S J 5 0 S T P C L K J A P I C G N T 5 1 I N T R 5 4 I G N N E J 5 5 A 2 0 M J 5 6 F E R R J 6 2 R S T D R V 5 7 E X T S W A P I ...

Page 222: ...9 DQ11 72 DQ12 73 DQ13 74 DQ14 75 DQ15 78 DQ16 79 DQ17 2 DQ18 3 DQ19 6 DQ20 7 DQ21 8 DQ22 9 DQ23 12 DQ24 13 DQ25 18 DQ26 19 DQ27 22 DQ28 23 DQ29 24 DQ30 25 DQ31 28 DQ32 29 NC 51 NC 80 NC 66 NC ZZ 64 BWE 87 GW 88 NC 30 NC 39 U49 S32K32 07 CADS CADV CPUADS L2CLK1 CADS CPUADS CADV CPUD3 CPUD0 CPUD1 CPUD2 L2CLK1 3 3V 3 3V 1 2 2 CX1 SCD1U CX2 SCD1U CX9 SCD1U ADD CX1 CX2 CX7 CX8 CX9 BE 0 7 CPUA 3 17 L2C...

Page 223: ...2 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 143 146 145 CN20 SDIMM144 C268 SC4D7U16V6ZY C261 SC4D7U16V6ZY MD32 MD33 3 3V 3 3V C271 SC4D7U16V6ZY MD 0 63 MA 2 11 MD0 MD1 MD 0 63 MA 2 11 3 3V 3 3 MAA0 MAA1 MD2 MD3 MD4 MD5 MD...

Page 224: ...5 INVAPMSEL0 5V 9 8 1 4 7 U41D SSHCT04 1 2 R61 33R3 1 2 R90 33R3 1 2 R64 33R3 VDD 1 VDD 8 VDD 14 VDD 26 VDD 32 XIN 2 XOUT 3 CPUEN1 5 CPU PCIEN 19 SEL 18 S1 15 S0 16 VSS 4 VSS 11 VSS 20 VSS 23 VSS 29 CPU0 6 CPU1 7 CPU2 9 CPU3 10 CPU4 12 CPU5 13 CPU6 17 PCI0 21 PCI1 22 PCI2 24 PCI3 25 PCI4 27 USB CLK 30 EPCI 28 IOCLK 31 REF0 34 REF1 33 U39 CY2263 1 2 R67 33R3 AMSTATE 1 2 R59 0R3 1 2 R60 33R3 1 2 R92...

Page 225: ...ND 10 U36 SSHCT373 5 6 1 4 4 7 U26B SSHC125 ID_CLK VR_U D BLVR AD24 LLED 5V 19 19 REMOVE U15 PAD CIRUIT MODIFY TPX1 TP 1 TPX2 TP 1 1 2 3 4 5 6 7 8 9 10 RP12 SRP10K 3_MODE ENAUDIO TH_CLK TH_RST DISABLELED MREQJ LIB MH FLASH_ON FDDIN HOTKEY GPIOWF1 AD31 AD30 AD28 AD26 AD25 AD27 AD29 FDDIN LIB MH VSW1 GPIORF1 5V 5V 2 2 3 4 17 20 21 24 3 12 14 16 19 16 23 9 13 12 AD 0 31 AD31 AD29 AD30 AD28 AD26 AD27 ...

Page 226: ... SB ADD DUMMY RESISTER TO PWRGOOD 23 24 24 1 2 BT1 BH 12 SA 0 15 4 C265 SCD1U 1 2 X1 XTAL 32 768KHZ A0 20 A1 19 A2 18 A3 17 A4 16 A5 15 A6 14 A7 13 A8 3 A9 2 A10 31 A11 1 A12 12 A13 4 A14 5 A15 11 A16 10 CE 30 VCC 8 VSS 24 VPP 9 DQ0 21 DQ1 22 DQ2 23 DQ3 25 DQ4 26 DQ5 27 DQ6 28 DQ7 29 WE 7 OE 32 A17 6 U52 28F020 1 SA0 HDD 5V CX30 SC3P50V3KN CX31 SC3P50V3KN 3 2 1 Q8 S2N3906 C266 SCD1U MEMW SD0 SD1 S...

Page 227: ... MCLK MDATA XCLK XDATA 5V 1 2 3 4 5 6 7 8 9 10 RP34 SRP10K SD 0 7 KROW6 KROW7 KROW8 SD 0 7 KROW1 KROW2 KROW3 KROW5 KROW6 5V 5V 5V 4 9 11 13 15 IOW IOR SA2 KBCS FS1 FS0 SD3 SD4 SD5 SD6 SD7 SD0 SD1 SD2 KROW1 KROW2 KROW3 KROW4 KROW5 SA2 IOR IOW TDATA TCLK KROW4 KROW7 KROW8 4 4 4 4 7 7 1 2 R74 10KR3 IRQ1 IRQ12 CLLED NLLED SLLED IRQ1 IRQ12 XCLK XDATA 5V TRACKSTICK CONN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ...

Page 228: ... D R A T E 1 M S E N 1 C S 0 S R I Q 1 2 4 9 D R A T E 0 M S E N 0 5 0 IOCHRDY 51 DACK1 52 DACK0 53 DRQ0 54 IRQ9 55 IRQ10 56 IRQ11 57 IRQ15 SIRQI1 58 VSSE 59 R12 A11 60 DTR2 A12 61 CTS2 A13 62 SOUT2 BOUT2 CFG0 IIRTX 63 RTS2 A14 64 SIN2 IRRX1 65 DSR2 IRRX2 IRQ12 66 DCD2 A15 67 RI1 68 DTR1 CFG1 69 CTS1 70 SOUT1 BOUT1 BOUT1 BADDR1 71 RTS1 BADDRO 72 SIN1 73 DSR1 74 DCD1 75 A F D D S T R B D E N S E L ...

Page 229: ... FDDDCHG 5V 5V 11 14 VCC 24 B0 2 A0 3 A1 4 B1 5 B2 6 A2 7 A3 8 B3 9 B4 10 A4 11 OEA 1 OEB 13 GND 12 B9 23 A9 22 A8 21 B8 20 B7 19 A7 18 A6 17 B6 16 B5 15 A5 14 U1 QQST3384 GND 1 IN 2 IN 3 EN 4 OUT 8 OUT 7 OUT 6 OUT 5 U23 TPS2013D 1 2 R115 10KR3 RDATA TRK0 WRTPRT EXTRDATA EXTTRK0 EXTWRTPRT FDDRDY 5V 5V FDD5V 5V 11 14 14 1 2 R114 33R3 BUSYP PINIT PSLCTIN PACK PPE PSLCT PPD1 PPD2 PPD3 PPD4 PPD5 PPD6 ...

Page 230: ...A10 SA11 SA12 SA13 SA14 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 4 23 4 9 10 11 15 4 8 9 HDD 5V HDD 5V THIS GOLDEN FINGER IS REVISED BY PEACH 9 24 IOCHRDY AEN IOW IOR BALE IRQ11 LA23 LA22 LA21 LA20 RSTDRV SA15 SA16 SD0 SD1 SD2 SD3 SD4 MEMR MEMW 4 4 4 4 4 4 4 4 4 4 24 4 IRQ10 RTCROMCS XSA17 XSA16 SBHE SA19 SA18 SA17 LA19 LA18 LA17 IRQ11 IRQ10 SBHE 4 4 4 4 4 4 4 4 4 8 8 1 2 3 4 5 6 7 8 9 10...

Page 231: ...12 IDE_D13 IDE_D14 IDE_D15 IDE_IOW IDE_IOR 4 1 2 R202 DUMMY R3 1 2 R198 0R3 1 2 R200 1KR3 1 2 R199 4K7R3 IDE_DACK1 SIRQI IRQ15 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_RDY 5V 5V 4 4 4 13 C93 SCD1U C92 SC10U16V 1 2 R175 4K7R3 1 2 R174 0R3 C104 SCD1U CD_AUDL RPM 3_MODE CDROM_LED IDE_A1 IDE_A0 CD_CS1 5V 11 8 12 15 CDROM 5V C103 SC10U16V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 2...

Page 232: ...V O C I R 7 9 V O C I L 8 0 O U T R 8 1 O U T L 8 2 A U X I R 8 3 A U X I L 8 4 L I N E R 8 5 L I N E L 8 6 A V D D 8 7 A V S S 8 8 V R E F I 8 9 V R E F O 9 0 M I N 9 1 M I C 9 2 A U X 2 R 9 3 A U X 2 L 9 4 T R E C L 9 5 T R E C R 9 6 S Y N S H R 9 7 S Y N S H L 9 8 S B F L T L 9 9 S B F L T R 1 0 0 U31 YMF715 1 2 R53 220KR3 C194 SCD01U C41 SC1U16V5ZY RSTDRV T R E C L T R E C R S B F L T L S B F ...

Page 233: ... 1 2 R6 47KR3 C178 C179 P N 80 10711 141 1 2 G4 GAP CLOSE LINE_OUT_L SPKR_L BATPRLED CHARGELED 3 3V 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CN12 SCON20 2 1 2 D8 S1N4148 CLLED SLLED NLLED SLED MEDIA_LED DISPLED 8 10 10 10 MIC_IN_C LINE_IN_L LINE_IN_R LINE_OUT_R SPKR_R 15 15 15 LINE_OUT_R SPEAKERRB CX35 SCD1U 1 2 RX12 2K2R3 1 2 C178 ST100U10VDK CX32 SCD1U C28 SC100P 1 2 R26 47KR3 SOUND...

Page 234: ... 3 7 M B D 1 1 1 3 8 M B D 1 2 1 4 0 M B D 1 3 1 4 1 M B D 1 4 1 4 3 M B D 1 5 1 4 4 RASB 123 CASBH 125 CASBL 126 WEB 124 P8 81 P9 82 P10 83 P11 84 P12 85 P13 86 P14 87 P15 88 ACTI 53 ENABKL 54 M 69 A20 199 ROMOE 200 CLK 201 A23 28 SERR 30 M V C C B 1 4 2 I V C C 1 8 1 C V C C 0 2 0 5 C V C C 1 2 0 6 C G N D 0 2 0 2 C G N D 1 2 0 8 RSET 55 PERR 29 A D 1 9 1 7 A D 2 0 1 6 A D 2 1 1 5 A D 2 2 1 4 A ...

Page 235: ...CD1U C18 SC10U16V 1 2 R147 33R3 C19 SCD1U C205 SCD1U 1 2 R154 33R3 C193 SC10U16V C196 SCD1U C192 SCD1U C200 SC10U16V 1 2 L6 HF70ACB VGAPWR CCFTPWR C81 SCD1U C31 SCD01U C199 SCD01U C191 SCD01U VAA 0 8 VWEA VRASA VAA0 VAA1 VAA2 VAA3 VMAD6 VMAD7 CVCC1 CVCC0 AVCC 17 17 17 VCASAL VCASAH VAA4 VAA5 VAA6 VAA7 VAA8 VMAD8 VMAD9 VRAMOE VCASAL VCASAH 17 17 VRAMOE VCASBL VCASBH VAA4 VAA5 VAA6 VAA7 VAA8 VMBD8 V...

Page 236: ...31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 CN6 JAE CONN80C R 0 7 SUD 0 7 PSHFCLK PLP R1 R2 R5 17 17 20 20 1 3 2 L13 ELKE101FA C159 SCD1U 1 2 R126 470R3 1 2 R15 330R3 1 2 L12 MLB321611 UD1 LD2 UD2 ID_CLK BLVR ID_DATA CCFT_ON BBT_QCHG PLED R6 SUD2 SUD1 SUD6 SUD5 5V CCFTPWR 5V 8 8 8 8 17 17 17 2...

Page 237: ... R162 10R3 FLM LP MOD PLFS PLP PMOD PLFS PLP PMOD 17 17 17 1 2 R157 22R3 1 2 R132 0R3 1 2 3 D5 BAV99LT1 HSYNC VSYNC 17 17 19 19 19 THESE COMPONENTS 68 00031 001 1 2 R40 10R3 1 2 R39 10R3 1 2 L14 BK2125HS330 1 2 L15 BK2125HS330 C17 SC47P C16 SC47P 1 2 3 D4 BAV99LT1 5V CRT_HS CRT_VS 19 19 LCD_DISPLAY 19 DISPLAY DISPLAY 3 3V 2 3 1 4 1 7 U13A SOLCX125M 8 1 2 R56 22R3 GPIORF1 LIB MH AD16 CPU_TH AD17 5V...

Page 238: ...AD20 123 A_CRST 124 A_CAD21 125 A_CAD22 126 A_CREQ 127 A_CAD23 128 GND 129 A_CC BE3 130 A_CAD24 131 A_CAD25 132 A_CAD26 133 A_CVS1 134 A_CINT 135 A_CSERR 136 A_CAUDIO 137 A_CSTSCHG 138 A_CCLKRUN 139 A_CCD2 140 A_CAD27 141 A_CAD28 142 VCC 143 A_CAD29 144 A_CAD30 145 A_RSVD 146 A_CAD31 147 VCCP 148 SPKROUT SUSPEND 149 LATCH 150 CLOCK 151 DATA 152 GND 153 IRQ3 INTA 154 IRQ4 INTB 155 IRQ5 156 I R Q 7 ...

Page 239: ...A_WE A_IREQ A_VS1 A_CE1 A_CE2 A_OE A_IORD A_IOWR A_WE A_IREQ A_VS1 A_VPP A_SLOT_VCC 5V B_VPP B_SLOT_VCC A_SLOT_VCC A_VPP 21 21 21 21 21 21 21 21 B_D15 B_A8 B_A9 B_A10 B_A11 B_A13 B_A14 B_A16 B_A17 B_A18 B_A19 B_A20 B_A21 A_D15 A_A8 A_A9 A_A10 A_A11 A_A13 A_A14 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 B_CE1 B_CE2 B_OE B_IORD B_IOWR B_WE B_IREQ B_VS1 B_CE1 B_CE2 B_OE B_IORD B_IOWR B_WE B_IREQ B_VS1 B_VPP...

Page 240: ... 2 C181 ST22U35VDM C71 SC1000P50V3KX C79 SC1000P50V3KX 3 3V DCBATOUT CX6 SC10U50V CX20 SC10U10V6JY CX21 SC10U10V6JY 1 2 1 4 7 U38A SSHC14 1 2 C77 ST100U10VDM C78 SCD1U 3 4 1 4 7 U38B SSHC14 PWRGOOD PWRGOOD 5V 5V CHARGER CONN 3 2 1 Q6 RN2424 1 2 3 Q3 2N7002 PWR_SW BT BTS ID BT 4 8 13 8 9 13 16 1 2 R135 10KR3 C29 SCD1U DISABLE BT BBL1 BBL2 BAT_USE BT 8 5VSB_DC ADD U1 RX5 CX5 5 6 4 1 4 7 U1XB TSHC02 ...

Page 241: ...SSHCT32 4 5 6 1 4 7 U45B SSHCT32 IOW RTCROMCS IOR RTCDS RTCRW 5V 5V 4 4 4 9 9 L Internal keyboard cntrler enable H Internal KBC disable L Internal RTC enable H Internal RTC disable L External I O APIC mode supported H Ext I O APIC mode not supported Must pull High Refer to CKT down left 1 2 R42 10KR3 1 2 R20 10KR3 1 2 R38 10KR3 1 2 R173 10KR3 1 2 R170 560R3 SPKR PHOLD TC KBCS RTCROMCS 4 4 4 9 8 1 ...

Page 242: ... TO PIN 201 202 C114 SC2K2P C124 SCD1U C123 SCD1U 3 3V CLOSE TO PIN 190 203 204 C239 SCD1U C243 SCD1U C245 SCD1U C116 SCD1U 3 3V 5V 3 3V C111 SC1U16V5ZY C258 SCD1U C36 SCD1U C247 SCD1U C206 SCD1U C219 SCD1U C220 SCD1U C95 SCD1U C26 SCD1U C170 SCD1U C273 SCD1U 5V HDD 5V 5V CX38 SCD1U CX39 SC10U16V HDD 5V CY1 SC4D7U16V6ZY CY2 SCD1U CY3 SC1000P50V3KX CLOSE TO PIN 156 CLOSE TO PIN 105 C230 SC4D7U16V6Z...

Page 243: ... initialization 14h System Timer 8254 testing initialization 18h DRAM refresh cycle testing Set default SS SP 0 400 1Ch CMOS shutdown byte test battery and check sum Note Several parts of the POST routine require the system to be in protected mode When returning to real mode from protected mode the processor is reset therefore POST is re entered In order to prevent re initialization of the system ...

Page 244: ...ice request 41h Assign Memory if device requested 44h Assign IRQ if device request 45h Enable command byte if device is OK 51h DownLoad keyboard matrix 50h Initialize Video display 4Ch ChipUp initialization for CPU clock checking 54h Process VGA shadow region 58h Set POST screen mode Graphic or Text Display Acer or OEM logo if necessary Display Acer copyright message if necessary Display BIOS seri...

Page 245: ...flash once and its head should be positioned 88h HDD testing parameter table setup 89h Get CPU MUX Note This routine is to identify the user set CPU frequency not CPU required frequency 90h Display POST status if necessary Change POST mode to default text mode 93h Rehook int1c for quiet boot 94h Initialize expansion ROM Shadow I O ROM if setup requests Build up free expansion ROM table A4h Initial...

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