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138
Chapter 4
0x36
Setup DRAM control register for normal operation and enable
PEI
chipset/MRC
0x37
Do ZQ calibration for DDR3
PEI
chipset/MRC
0x38
Perform final Dra/Drb programming, Set the mode of operation
for the memory channels
PEI
chipset/MRC
0x39
Set Enhanced addressing mode for each channel
PEI
chipset/MRC
0x40
Perform steps required after JEDEC init
PEI
chipset/MRC
0x41
Program the receive enable reference timing control register
PEI
chipset/MRC
0x42
Post receive enable initialization
PEI
chipset/MRC
0x43
Enable sense amps. Reset read/write DQS pointers
PEI
chipset/MRC
0x44
Perform ME steps
PEI
chipset/MRC
0x45
Clear DRAM initialization bit in the ICH.
PEI
chipset/MRC
0x46
Program Thermal Management
PEI
chipset/MRC
0x47
Program TS on DIMM
PEI
chipset/MRC
0x48
Program TS on Board
PEI
chipset/MRC
0xAF
Exit MRC
PEI
chipset/MRC
0xE0
#define MEM_ERR_BAD_DIMM (S11)
PEI
chipset/MRC
0xE1
#define MEM_ERR_ECC_DIMM (S06)
PEI
chipset/MRC
0xE2
#define MEM_ERR_SIDES (S07)
PEI
chipset/MRC
0xE3
#define MEM_ERR_WIDTH (S08, S10)
PEI
chipset/MRC
0xE4
#define MEM_ERR_TRFC (FindTrasTrpTrcd)
PEI
chipset/MRC
0xE5
#define MEM_ERR_CAS_LATENCY (S12, S13)
PEI
chipset/MRC
0xE6
#define MEM_ERR_REFRESH (ProgDrt)
PEI
chipset/MRC
0xE7
#define MEM_ERR_BL8 (S14)
PEI
chipset/MRC
0xE9
#define MEM_ERR_FREQUENCY (findTCLTacTClk, S13,
S12, ProgramGraphicsFrequency, ProgMchOdt,
GetPlatformData)
PEI
chipset/MRC
0xEA
#define MEM_ERR_SIZE (S14)
PEI
chipset/MRC
0xEC
#define MEM_ERR_TRAS (FindTrasTrpTrcd)
PEI
chipset/MRC
0xED
#define MEM_ERR_TRP (FindTrasTrpTrcd)
PEI
chipset/MRC
0xEE
#define MEM_ERR_TRCD (FindTrasTrpTrcd)
PEI
chipset/MRC
0xEF
#define MEM_ERR_TWR (FindTrasTrpTrcd)
PEI
chipset/MRC
0xF0
#define MEM_ERR_RCVEN_FINDLOW
(CalibrateRcvenForGroup)
PEI
chipset/MRC
0xF1
#define MEM_ERR_RCVEN_FINDEDGE
(CalibrateRcvenForGroup)
PEI
chipset/MRC
0xF2
#define MEM_ERR_RCVEN_FINDPREAMBLE
(CalibrateRcvenForGroup)
PEI
chipset/MRC
0xF6
#define MEM_ERR_RCVEN_PREAMBLEEDGE
(CalibrateRcvenForGroup)
PEI
chipset/MRC
0xF3
#define MEM_ERR_RCVEN_FINDCENTER
(CalibrateRcvenForGroup)
PEI
chipset/MRC
0xF4
#define MEM_ERR_TYPE (S11, S04)
PEI
chipset/MRC
0xF5
#define MEM_ERR_RAWCARD (S11)
PEI
chipset/MRC
0xFA
#define MEM_ERR_SFF (ProgWrioDll)
PEI
chipset/MRC
0xFB
#define MEM_ERR_THERMAL (ProgramThrottling)
PEI
chipset/MRC
POST Code
Function
Phase
Component
Summary of Contents for 6930 6082 - Aspire - Core 2 Duo GHz
Page 6: ...VI ...
Page 10: ...X Table of Contents ...
Page 42: ...32 Chapter 1 ...
Page 56: ...46 Chapter 2 ...
Page 91: ...Chapter 3 81 4 Grasp the module by the right side and lift up to remove ...
Page 99: ...Chapter 3 89 7 Disconnect the Mic cable and remove the LCD bezel ...
Page 110: ...100 Chapter 3 4 Replace the ten securing screws and screw caps on the LCD bezel ...
Page 112: ...102 Chapter 3 3 Connect fan cable to the mainboard as shown ...
Page 126: ...116 Chapter 3 7 Turn the computer over and replace the ten screws as shown ...
Page 234: ...224 Appendix B ...
Page 236: ...226 Appendix C ...