MC96FR116C
36
November, 2018 Rev.1.8
7.14 I2C CHARACTERISTICS
The following table and figure show the timing codition of SDA and SCL bus lines for I
2
C bus devices.
Parameter
Symbol
STANDARD MODE
FAST MODE
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
0
100
0
400
kHz
Hold time after (repeated) START
condition. After this period, the first clock
pulse is generated
t
HD;STA
4.0
-
0.6
-
Us
LOW period of the SCL clock
t
LOW
4.7
-
1.3
-
Us
HIGH period of the SCL clock
t
HIGH
4.0
-
0.6
-
us
Setup time for a repeated START
condition
t
SU;STA
4.7
-
0.6
-
us
Data hold time
t
HD;DAT
0
3.45
0
0.9
us
Data setup time
t
SU;DAT
100
-
100
-
ns
Clock/data fall time
t
F
0
300
0
300
ns
Clock/data rise time
t
R
0
1000
0
300
ns
Setup time for STOP condition
t
SU;STO
4.0
-
0.6
-
us
Bus free time between a STOP and
START condition
t
BUF
4.7
-
1.3
-
us
Table 7-15 Timing characteristics of I
2
C
SDA
SCL
t
LOW
t
F
t
HD;STA
t
R
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
t
SU;STA
t
HD;DAT
t
BUF
t
R
t
SU;STO
S
Sr
S
P
Figure 7-2 Timing diagram of I
2
C
