Abov MC96F8204 Series User Manual Download Page 99

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MC96F8204

ABOV Semiconductor Co., Ltd.

Figure 11.9

Input Capture Mode Operation for Timer 0

Figure 11.10

Express Timer Overflow in Capture Mode

T0CNT

Interrupt

Request

(FLAG10)

Interrupt Interval Period = FF

+01

+FF

+01

+YY

+01

Ext. EINT10 PIN

Interrupt

Request

(T0IFR)

T0CNT Value

Interrupt

Request

(FLAG10)

TIME

n-2

n-1

Interrupt Interval Period

Count Pulse Period
P

Up-count

T0CDR Load

Ext. EINT10 PIN

Summary of Contents for MC96F8204 Series

Page 1: ...2 0 TA 0 50 C Internal 200kHz RC Oscillator 3 0 TA 20 85 C Watchdog Timer RC Oscillator 5kHz Peripheral Features 12 bit Analog to Digital Converter 8 inputs USART UART SPI 1set I2C 8 bit x 1 ch 16 bit...

Page 2: ...1 3 2016 09 08 Remove packages the 20 QFN 16 TSSOP 16 QFN 8 PDIP Modify package from 16 SOP to 16 SOPN 1 4 2016 12 21 Revised this book Fix typos of T0 T1 T2 Version 1 4 Published by FAE team 2016 ABO...

Page 3: ...e I O basic interval timer watchdog timer 8 16 bit timer counter 16 bit PPG output watch timer USART UART SPI I2C 12 bit A D converter Flash CRC Checksum Generator on chip POR LVR LVI on chip oscillat...

Page 4: ...1 4V Low Voltage Reset 14 level detect 1 60 2 05 2 15 2 25 2 37 2 50 2 65 2 82 3 01 3 22 3 47 3 76 4 10 4 51V Low Voltage Indicator 13 level detect 2 05 2 15 2 25 2 37 2 50 2 65 2 82 3 01 3 22 3 47 3...

Page 5: ...D interface uses two wire interfacing between PC and MCU which is attached to user s system The OCD can read or change the value of MCU internal memory and I O peripherals And the OCD also controls MC...

Page 6: ...6 MC96F8204 ABOV Semiconductor Co Ltd 1 3 3 Programmer Single programmer E PGM It programs MCU device directly DSDA VDD DSCL VSS Figure 1 2 E PGM Single writer...

Page 7: ...s ISP In System Programming It does not require additional H W except developer s target system Gang programmer E GANG4 and E GANG6 It can run PC controlled mode It can run standalone without PC contr...

Page 8: ...ming The MC96F8204 needs only four signal lines including VDD and VSS pins for programming FLASH with serial protocol Therefore the on board programming is possible if the programming signal lines are...

Page 9: ...er programming To application circuit DSCL I DSDA I O R1 2k 5k To application circuit R2 2k 5k VDD VSS E PGM E GANG4 E GANG6 NOTE 1 In on board programming mode very high speed signal will be provided...

Page 10: ...1 channel 8 bit CORE M8051 General purpose I O 18 ports normal I O Watchdog timer 1 channel 8 bit 5kHz internal RC OSC Basic interval timer 1 channel 8 bit Timer Counter 1 channel 8 bit 2 channels 16...

Page 11: ...0 pin as DSCL DSDA Figure 3 1 MC96F8204D 20SOP TSSOP Pin Assignment MC96F8204M 16 SOPN 1 2 3 4 14 13 16 15 VDD P06 AN6 SS XIN SXIN P05 AN5 AVREF EC1 RESETB VSS P07 AN7 SCK XOUT SXOUT P01 AN1 EINT1 RX...

Page 12: ...push pull output or an input with pull up resistor by software control when the 10 pin package is used Figure 3 3 MC96F8104S 10SSOP Pin Assignment MC96F8104M 8 SOP 1 2 3 4 6 5 8 7 VDD VSS P02 AN2 EINT...

Page 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...

Page 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...

Page 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...

Page 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...

Page 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...

Page 18: ...10 Pin 8 Pin package Input P21 EINT0 I O External interrupt input Input P00 AN0 TXD MOSI DSDA EINT1 I O External interrupt input Input P01 AN1 RXD MISO DSCL EINT10 I O External interrupt and Timer 0 c...

Page 19: ...AN6 SS SXIN XOUT P07 AN7 SCK SXOUT SXIN I O Sub oscillator pins Input P06 AN6 SS XIN SXOUT P07 AN7 SCK XOUT VDD VSS Power input pins Table 5 1 Normal Pin Description Concluded NOTE 1 The P16 P17 and P...

Page 20: ...VDD OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC E...

Page 21: ...1 0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT o...

Page 22: ...Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond...

Page 23: ...rrent IAN AVREF 5 12V 2 uA A DC Current IADC Enable VDD 5 12V 1 2 mA Disable 0 1 uA Table 7 3 A D Converter Characteristics NOTE 1 Zero offset error is the difference between 000000000000 and the conv...

Page 24: ...levels except 1 60V 1 60 1 79 V 1 90 2 05 2 20 2 00 2 15 2 30 2 10 2 25 2 40 2 22 2 37 2 52 2 35 2 50 2 65 2 45 2 65 2 85 2 62 2 82 3 02 2 81 3 01 3 21 3 02 3 22 3 42 3 27 3 47 3 67 3 46 3 76 4 06 3 8...

Page 25: ...uency Internal RC Oscillator Characteristics TA 40 C 85 C VDD 1 8V 5 5V VSS 0V Parameter Symbol Conditions MIN TYP MAX Unit Frequency fLFIRC 200 kHz Tolerance VDD 2 2 5 5V TA 20 C to 85 C 3 0 Clock Du...

Page 26: ...dback resistor RX1 XIN VDD XOUT VSS TA 25 C VDD 5V 600 1200 2000 k RX2 SXIN VDD SXOUT VSS TA 25 C VDD 5V 2500 5000 10000 k Supply Current IDD1 RUN fXIN 12MHz VDD 5V 10 3 0 6 0 mA fHFIRC 8MHz 2 0 4 0 f...

Page 27: ...ST VDD 5V 10 us Interrupt input high low width tIWH tIWL All interrupt VDD 5V 200 ns External Counter Input High Low Pulse Width tECWH tECWL EC1 EC2 VDD 5V 200 External Counter Transition Time tREC tF...

Page 28: ...ulse Width tSCKH tSCKL Internal SCK source 140 Input Clock High Low Pulse Width External SCK source 140 First Output Clock Delay Time tFOD Internal External SCK source 200 Output Clock Delay Time tDS...

Page 29: ...e to input data valid tS2 590 Output data hold after clock rising edge tH1 tCPU 50 tCPU Input data hold after clock rising edge tH2 0 Serial port clock High Low level width tHIGH tLOW 470 tCPU x 8 970...

Page 30: ...ulse Width tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSPSU 4 0 0 6 Stop Condition Hold Time tSP...

Page 31: ...er Active VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tWAIT VDDDR Figur...

Page 32: ...Frequency fPGM 0 4 MHz Endurance of Write Erase NFWE 10 000 times Flash Data Retention Time tRT 10 years Table 7 15 Internal Flash Rom Characteristics NOTE 1 During a flash operation SCLK 1 0 of SCCR...

Page 33: ...n frequency 2 0V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 Ceramic Oscillator Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 External Clock XIN input frequency 1 8V 5 5V 0 4 4 2 MHz 2 7...

Page 34: ...llator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN input frequency 32 100 kHz Table 7 18 Sub Clock Oscillator Characteristics...

Page 35: ...minimum oscillator voltage range 10 ms External Clock fXIN 0 4 to 12MHz XIN input high and low width tXH tXL 41 7 1250 ns Table 7 19 Main Oscillation Stabilization Characteristics tXH tXL XIN 0 2VDD...

Page 36: ...7 5 5 12 0MHz fXIN 0 4 to 12MHz Ceramic Supply voltage V 4 2MHz 2 0 0 4MHz 2 7 5 5 12 0MHz fXIN 0 4 to 12MHz Crystal Supply voltage V 4 2MHz Figure 7 14 Operating Voltage Range Main OSC 1 8 5 5 32 768...

Page 37: ...commended Circuit and Layout for Main X TAL OSC MC96F8204 I O VSS VDD High Current Part Infrared LED FND 7 Segment etc 0 01uF VCC 0 1uF This 0 1uF capacitor should be within 1cm from the VDD pin of MC...

Page 38: ...ecommended C2 47uF 25V more The R1 and C2 should be as close by the C3 as possible 3 The C3 capacitor is used for temperature compensation because an electrolytic capacitor becomes worse characteristi...

Page 39: ...section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents mean 3 and mean 3 resp...

Page 40: ...nt 0 00 0 20 0 40 0 60 0 80 1 00 1 20 1 40 1 60 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V mA X tal 12MHz 40 X tal 12MHz 25 X tal 12MHz 85 HFIRC 8MHz 40 HFIRC 8MHz 25 HFIRC 8MHz 85 0 0 10 0 20 0 30 0 40 0 50...

Page 41: ...Ltd Figure 7 23 SUB RUN IDD3 Current Figure 7 24 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85 0 0 5 0 10 0 15 0 20 0 25 0 2 5V 3 0V 3...

Page 42: ...42 MC96F8204 ABOV Semiconductor Co Ltd Figure 7 25 STOP IDD5 Current 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85...

Page 43: ...e has just 4k bytes program memory space Figure 8 1 shows the map of the lower part of the program memory After reset the CPU begins execution from location 0000H Each interrupt is assigned a fixed lo...

Page 44: ...44 MC96F8204 ABOV Semiconductor Co Ltd FFFFH 0000H 4Kbytes 0FFFH Figure 8 1 Program Memory NOTE 1 4 Kbytes Including Interrupt Vector Region...

Page 45: ...cupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 8 3 The lowest 32 byte...

Page 46: ...Bytes 07H 00H 8 Bytes R7 R6 R5 R4 R3 R2 R1 R0 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4...

Page 47: ...8 3 Extended SFR Area This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit 0000H Extended Special Function Register Indirect Addressing 5050H 505FH Not u...

Page 48: ...W FCDIN 0C8H OSCCR LIFSR ADCDRL ADCDRH 0C0H EIFLAG P2 P2IO P2PU P2OD 0B8H IP XTFLSR 0B0H T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH 0A8H IE IE1 IE2 IE3 P1 P1IO P1PU P1OD 0A0H ADCCRL ADCCRH EO EIPOL0 EIPO...

Page 49: ...emiconductor Co Ltd 8 4 2 Extended SFR Map Summary 00H 8H 01H 9H 02H 0AH 03H 0BH 04H 0CH 05H 0DH 06H 0EH 07H 0FH 5058H FCDRL 5050H FCSARH FCEARH FCSARM FCEARM FCSARL FCEARL FCCR FCDRH Table 8 2 XSFR M...

Page 50: ...0 0 0 0 8FH P0 Function Selection Middle Register P0FSRM R W 0 0 0 0 90H Timer 0 Control Register T0CR R W 0 0 0 0 0 0 91H Timer 0 Counter Register T0CNT R 0 0 0 0 0 0 0 0 92H Timer 0 Data Register T...

Page 51: ...er 3 IE3 R W 0 0 0 0 ACH P1 Data Register P1 R W 0 0 0 0 0 0 0 0 ADH P1 Direction Register P1IO R W 0 0 0 0 0 0 0 0 AEH P1 Pull up Resistor Selection Register P1PU R W 0 0 0 0 0 0 0 0 AFH P1 Open drai...

Page 52: ...Converter Data Low Register ADCDRL R x x x x x x x x CFH A D Converter Data High Register ADCDRH R x x x x x x x x D0H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D1H Reserved D2H Reserved D...

Page 53: ...W 0 0 0 0 0 0 0 1 EEH I2C SCL Low Period Register I2CSCLR R W 0 0 1 1 1 1 1 1 EFH I2C SCL High Period Register I2CSCHR R W 0 0 1 1 1 1 1 1 F0H B Register B R W 0 0 0 0 0 0 0 0 F1H I2C Slave Address 1...

Page 54: ...3H Flash CRC End Address Middle Register FCEARM R W 0 0 0 0 0 0 0 0 5054H Flash CRC Start Address Low Register FCSARL R W 0 0 0 0 0 0 0 0 5055H Flash CRC End Address Low Register FCEARL R W 0 0 0 0 0...

Page 55: ...W R W R W R W R W R W Initial value 00H B B Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5...

Page 56: ...0H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set...

Page 57: ...a system reset 9 2 3 Pull up Resistor Selection Register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU The pull up regis...

Page 58: ...ction High Register P0FSRM 8FH R W 00H P0 Function Selection Mid Register P0FSRL 96H R W 00H P0 Function Selection Low Register P1 ACH R W 00H P1 Data Register P1IO ADH R W 00H P1 Direction Register P...

Page 59: ...Data P0IO P0 Direction Register 88H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Input 1 Output N...

Page 60: ...gure Debounce of P03 Port 0 Disable 1 Enable P02DB Configure Debounce of P02 Port 0 Disable 1 Enable P01DB Configure Debounce of P01 Port 0 Disable 1 Enable P00DB Configure Debounce of P00 Port 0 Disa...

Page 61: ...1 0 P06 Function Select P0FSRH1 P0FSRH0 Description 0 0 I O Port SS function possible when input 0 1 AN6 Function 1 0 XIN Function 1 1 SXIN Function NOTE 1 The pull up resistor of P06 P07 is automatic...

Page 62: ...3 2 P05 Function select P0FSRM3 P0FSRM2 Description 0 0 I O Port EC1 function possible when input 0 1 AN5 Function 1 0 AVREF Function 1 1 Not used P0FSRM 1 0 P04 Function select P0FSRM1 P0FSRM0 Descr...

Page 63: ...AN3 Function 1 0 T2O PWM2O Function 1 1 SCL Function P0FSRL 5 4 P02 Function Select P0FSRL5 P0FSRL4 Description 0 0 I O Port EINT11 function possible when input 0 1 AN2 Function 1 0 T1O PWM1O Function...

Page 64: ...l value 00H P1 7 0 I O Data P1IO P1 Direction Register ADH 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direct...

Page 65: ...SR1 P1FSR0 R W R W R W R W R W Initial value 00H P1FSR4 P14 Function select 0 I O Port 1 SCK Function P1FSR3 P13 Function select 0 I O Port 1 RXD MISO Function P1FSR2 P12 Function select 0 I O Port 1...

Page 66: ...P2 P2 P2 Data Register C4H 7 6 5 4 3 2 1 0 P21 P20 R W R W Initial value 00H P2 1 0 I O Data P2IO P2 Direction Register C5H 7 6 5 4 3 2 1 0 P21IO P20IO R W R W Initial value 00H P2IO 1 0 P2 Data I O...

Page 67: ...interrupts are enabled through four pair of interrupt enable registers IE IE1 IE2 IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall cont...

Page 68: ...nterrupt 18 Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 Interrupt 4 Interrupt 10 Interrupt 16...

Page 69: ...nterrupt polarity 1 register EIPOL1 as shown in Figure 10 1 Also each external interrupt source has enable disable bits The external interrupt flag register EIFLAG provides the status of external inte...

Page 70: ...IFR Reserved USART Rx USART Tx Level 0 Level 1 Level 2 Level 3 IE1 Reserved ADC Reserved WT WDT BIT IE3 ADCIFR WDTIFR BITIFR Reserved IE0 Reserved Reserved EINT10 EIFLAG 2 FLAG10 EIPOL1 EINT11 EIFLAG...

Page 71: ...rupt INT9 IE1 3 10 Maskable 004BH USART Tx Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 1 INT11 IE1 5 12 Maskable 005BH INT12 IE2 0 13 Maskable 0063H T0 Match Interrupt INT13 IE2 1 14 Ma...

Page 72: ...t instruction it needs 3 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI Once an interrupt request is generate...

Page 73: ...of Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Flag Register Command Next Instruction Next Instruction After executing n...

Page 74: ...than INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served after th...

Page 75: ...aving Restore Process Diagram and Sample Source Main Task Saving Register Restoring Register Interrupt Service Task INTxx PUSH PSW PUSH DPL PUSH DPH PUSH B PUSH ACC Interrupt_Processing POP ACC POP B...

Page 76: ...cted the lower 8 bit of interrupt vector INT_VEC is decided M8051W core makes interrupt acknowledge at the first cycle of a command and executes long call to jump to interrupt service routine NOTE 1 c...

Page 77: ...en the external interrupt generating condition is satisfied The flag is cleared when the interrupt service routine is executed Alternatively the flag can be cleared by writing 0 to it 10 12 4 External...

Page 78: ...upt polarity 0 register EIPOL0 external interrupt flag register EIFLAG and external interrupt polarity 1 register EIPOL1 10 12 7 Register Description for Interrupt IE Interrupt Enable Register A8H 7 6...

Page 79: ...0E INT9E INT7E R W R W R W R W Initial value 00H INT11E Enable or Disable External interrupt 1 EINT1 0 Disable 1 Enable INT10E Enable or Disable USART Tx interrupt 0 Disable 1 Enable INT9E Enable or D...

Page 80: ...tch Interrupt 0 Disable 1 Enable INT13E Enable or Disable Timer 0 Match Interrupt 0 Disable 1 Enable IE3 Interrupt Enable Register 3 ABH 7 6 5 4 3 2 1 0 INT22E INT21E INT20E INT18E R W R W R W R W Ini...

Page 81: ...IP1 IP0 R W R W R W R W R W R W Initial value 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R W R W R W R W R W R W Initial value 00H IP 5 0 IP1 5 0 Select In...

Page 82: ...s 1 The flag is cleared by writing a 0 to the bit or automatically cleared by INT_ACK signal Writing 1 has no effect 0 External Interrupt 0 1 10 11 12 not occurred 1 External Interrupt 0 1 10 11 12 oc...

Page 83: ...ely The main sub clock can be also obtained from the external oscillator In this case it is necessary to put the external clock signal into the XIN SXIN pin and open the XOUT SXOUT pin The default sys...

Page 84: ...1 1 1 2 1 4 1 8 M U X HFIRCS 2 0 fLFIRC System Clock Gen Core System Peripheral SCLK fx BIT WDT BIT overflow WDTRC OSC 5KHz WDTRC Stabilization Time Generation M U X WDT clock 256 BIT clock fx 4096 fx...

Page 85: ...ists of System and clock control register oscillator control register LFIRC frequency selection register and X tal filter selection register 11 1 5 Register Description for Clock Generator SCCR System...

Page 86: ...ternal Main Oscillator 0 Disable operation of X TAL 1 Enable operation of X TAL SCLKE Control the Operation of the External Sub Oscillator 0 Disable operation of SX TAL 1 Enable operation of SX TAL NO...

Page 87: ...n read 10101b Write 0x15 to these bits with valid XRNS 2 0 Other values Write is ignored XRNS 2 0 External Main Oscillator Range selection This bit is effective only when the fXIN is selected for syst...

Page 88: ...atures During Power On BIT gives a stable clock generation time On exiting Stop mode BIT gives a stable clock generation time As timer function timer interrupt occurrence 11 2 2 Block Diagram BIT Cloc...

Page 89: ...5 4 3 2 1 0 BITIFR BITCK1 BITCK0 BCLR BCK2 BCK1 BCK0 R W R W R W R W R W R W R W Initial value 01H BITIFR When BIT Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clea...

Page 90: ...up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equa...

Page 91: ...Name Address Direction Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch Dog Timer Control Register Table 11 3...

Page 92: ...lue 1 NOTE 1 Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT Op...

Page 93: ...able to be alive and so WT can continue the operation The watch timer counter circuits is composed of 21 bit counter Low 14 bit is binary counter and high 7 bit is auto reload counter in order to rais...

Page 94: ...TCR can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Timer WTCNT Watch...

Page 95: ...his bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK 2...

Page 96: ...The timer counter 0 can be clocked by an internal The clock source is selected by clock selection logic which is controlled by the clock selection bits T0CK 2 0 TIMER 0 clock source fX 2 4 8 32 128 51...

Page 97: ...is automatically cleared by match signal It can be also cleared by software T0CC P r e s c a l e r fx M U X fx 2 T0CNT 8Bit fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T0CK 2 0 T0EN 8 bit Timer 0 Counter...

Page 98: ...to T0CDR According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of course the EINT10 pin must be set to an input port T0CDR and T0DR are in the same address In the capt...

Page 99: ...ow in Capture Mode T0CNT Interrupt Request FLAG10 XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT10 PIN Interrupt Request T0IFR FFH FFH YYH 00H 00H 00H 00H 00H T0CNT Value Interrupt Req...

Page 100: ...T0MS Figure 11 11 8 bit Timer 0 Block Diagram 11 5 5 Register Map Name Address Direction Default Description T0CR 90H R W 00H Timer 0 Control Register T0CNT 91H R 00H Timer 0 Counter Register T0DR 92...

Page 101: ...R R Initial value 00H T0CNT 7 0 T0 Counter T0DR Timer 0 Data Register 92H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R W R W R W R W R W R W R W R W Initial value FFH T0DR 7 0 T0...

Page 102: ...Timer counter mode 1 Capture mode The match interrupt can occur T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1...

Page 103: ...PWM wave form through PWMnO port in the PPG mode TnEN P0FSRL 5 4 T1 P0FSRL 7 6 T2 TnMS 1 0 TnCK 2 0 Timer 1 2 1 10 10 00 XXX 16 Bit Timer Counter Mode 1 00 00 01 XXX 16 Bit Capture Mode 1 10 10 10 XX...

Page 104: ...t block A Match Buffer Register A Reload Pulse Generator TnO R TnEN 3 TnCK 2 0 2 TnMS1 TnMS0 TnCC 0 0 X TnCK2 TnCRL X ADDRESS 98H B0H INITIAL VALUE 0000_0000B TnCK1 TnCK0 TnIFR RLDnEN TnPOL TnECE Tn C...

Page 105: ...setting the external interrupt EINT11 EINT12 function is chosen Of course the EINT11 EINT12 pin must be set as an input port A Match TnCC TnEN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512 fx 204...

Page 106: ...Capture Mode TnCNTH L Interrupt Request FLAG1n XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H TnCNTH L Value Inter...

Page 107: ...512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter TnCNTH TnCNTL 16 bit B Data Register TnBDRH TnBDRL Clear B Match Edge Detector TnECE ECn Buffer Register B Comparator 16 bit A Data Register TnADRH TnA...

Page 108: ...nBDRH L 5 TnADRH L PWMnO A Match 2 TnBDRH L TnADRH L PWMnO A Match 3 TnBDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 M 0 Timer n clock Counter TnADRH L Tn Interrupt PWMnO B Match One shot Mode TnMS 10b and...

Page 109: ...etector TnECE ECn fx 1 To other block TnCK 2 0 3 To interrupt block A Match TnCC TnEN RLDnEN A Match TnCC TnEN RLDnEN NOTE 1 The TnEN is automatically cleared to logic 0 after one pulse is generated a...

Page 110: ...W Initial value FFH TnADRH 7 0 Tn A Data High Byte TnDRL Timer n A Data Low Register 9AH B2H Where n 1 and 2 7 6 5 4 3 2 1 0 TnADRL7 TnADRL6 TnADRL5 TnADRL4 TnADRL3 TnADRL2 TnADRL1 TnADRL0 R W R W R W...

Page 111: ...mer n disable 1 Timer n enable Counter clear and start TnMS 1 0 Control Timer n Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode TnO toggle at A match 0 1 Capture mode The A match interru...

Page 112: ...rs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 Tn Interrupt no generation 1 Tn Interrupt generation RLDnEN Control Timer n Reload...

Page 113: ...et to xx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion status bit AFLAG...

Page 114: ...Input Pins M U X AN0 Reference Voltage AVREF VSS AN1 AN2 AN7 VDD19 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X REFSEL TRIG ADST T1 A match signal Figure 11 20 12 bit ADC B...

Page 115: ...DCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 AD...

Page 116: ...ADCCRH SET ADCCRL AFLAG 1 Converting START READ ADCDRH L ADC END Select ADC Clock and Data Align Bit ADC enable Select AN Input Channel Start ADC Conversion If Conversion is completed AFLAG is set 1 a...

Page 117: ...verter Control Low Register ADCDRH CFH R xxH A D Converter Data High Register ADCDRL CEH R xxH A D Converter Data Low Register Table 11 9 ADC Register Map 11 7 6 ADC Register Description The ADC regis...

Page 118: ...M4 ADDL8 R R R R R R R R Initial value xxH ADDM 11 4 MSB align A D Converter High Data 8 bit ADDL 11 8 LSB align A D Converter High Data 4 bit ADCDRL A D Converter Data Low Register CEH 7 6 5 4 3 2 1...

Page 119: ...write 0 to this bit or auto clear by INT_ACK signal 0 ADC Interrupt no generation 1 ADC Interrupt generation TRIG A D Trigger Signal Selection The ADC module is automatically disabled at stop mode 0...

Page 120: ...sion start 0 No effect 1 Trigger signal generation for conversion start REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State...

Page 121: ...ck generator transmitter and receiver The clock generation logic consists of synchronization logic for external clock input used by synchronizing or SPI slave operation and the baud rate generator for...

Page 122: ...r Transmit Shift Register TXSR USTDR USTTX8 Tx USTP 1 0 M U X LOOPS TXC TXCIE DRIE DRE Empty signal To interrupt block INT_ACK Clear RXC RXCIE WAKEIE WAKE At Stop mode To interrupt block SCLK fx Syste...

Page 123: ...e speed mode is controlled by the DBLS bit in the USTCR2 register The MASTER bit in USTCR3 register controls whether the clock source is internal master mode output pin or external slave mode input pi...

Page 124: ...e operation When synchronous or SPI mode is used the SCK pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCK clock...

Page 125: ...top bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle...

Page 126: ...one complete frame according to the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode the ninth bit must be written to the USTTX8 bit in USTC...

Page 127: ...de or can be configured as SS output pin in master mode This can be done by setting USTSSEN bit in USTCR3 register 11 8 9 1 UART Receiving RX data When UART is in synchronous or asynchronous operation...

Page 128: ...The FE flag is 0 when the stop bit was correctly detected as 1 and the FEn flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions betwe...

Page 129: ...ng bits and removing the noise of RXD pin The next figure illustrates the sampling process of the start bit of an incoming frame The sampling rate is 16 times of the baud rate in normal mode and 8 tim...

Page 130: ...the received bit is considered to a logic 0 and if more than 2 samples have high levels the received bit is considered to a logic 1 The data recovery process is then repeated until a complete frame i...

Page 131: ...s MOSI for compatibility to other SPI devices 11 8 11 SPI Clock Formats and Timing To accommodate a wide variety if synchronous serial peripherals from different manufacturers the USART has a clock po...

Page 132: ...OSI inputs respectively At the second SCK edge the USART shifts the second data bit value out to the MOSI and MISO outputs of the master and slave respectively Unlike the case of CPHA 1 when CPHA 0 th...

Page 133: ...o the MOSI and MISO output of the master and slave respectively When CPHA 1 the slave s SS input is not required to go to its inactive high level between transfers Because the SPI logic reuses the USA...

Page 134: ...U X LOOPS TXC TXCIE DRIE DRE Empty signal To interrupt block INT_ACK Clear RXC Baud Rate Generator USTBD TXE SCLK fx System clock MISO MOSI M U X MASTER D E P FXCH SCK SCK Control MASTER RXE To interr...

Page 135: ...eration Register DDH 7 6 5 4 3 2 1 0 USTBD7 USTBD6 USTBD5 USTBD4 USTBD3 USTBD2 USTBD1 USTBD0 R W R W R W R W R W R W R W R W Initial value FFH USTBD 7 0 The value in this register is used to generate...

Page 136: ...in a frame USTS2 USTS1 USTS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 1 1 9 bit Other values Reserved ORD This bit is in the same bit position with USTS1 The MSB of the data byte...

Page 137: ...XC is inhibited use polling 1 When RXC is set request an interrupt WAKEIE Interrupt enable bit for Asynchronous Wake in STOP mode When device is in stop mode if RXD goes to Low level an interrupt can...

Page 138: ...ode 1 SCK is active while any frame is on transferring USTSSEN This bit controls the SS pin operation only SPI mode 0 Disable 1 Enable The SS pin should be a normal input FXCH SPI port function exchan...

Page 139: ...flag can be used to generate a RXC interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RXD pin is detected low w...

Page 140: ...A L B U S L I N E SCLK fx System clock SDA SCL I2CDR Rx VSS N ch VSS N ch SCL Out Controller SDA In Out Controller SDA Hold Time Register I2CSDHR SCL Low Period Register I2CSCLR SCL High Period Regis...

Page 141: ...the master to release the bus lines so that other devices can use it A high to low transition on the SDA line while SCL is high defines a START S condition A low to high transition on the SDA line whi...

Page 142: ...byte of data until it has performed some other function it can hold the clock line SCL LOW to force the master into a wait state Data transfer then continues when the slave is ready for another byte o...

Page 143: ...H by the slave And also when a slave addressed by a master is unable to receive more data bits the slave receiver must release the SDA line Data Packet The master can then generate either a STOP condi...

Page 144: ...rtest clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition Arbitration takes place on the SDA line while the SCL line is at the HI...

Page 145: ...ng edge of SCL If SDA should change in the middle of SCL LOW period load half the value of I2CSCLR to the I2CSDHR 5 Set the STARTC bit in I2CCR This transmits a START condition And also configure how...

Page 146: ...nerates TEND interrupt I2C can choose one of the following cases regardless of the reception of ACK signal from slave 1 Master receives ACK signal from slave so continues data transfer because slave c...

Page 147: ...or can be operate as an addressed slave To operate as a slave when the MLOST bit in I2CSR is set the ACKEN bit in I2CCR must be set and the received 7 bit address must equal to the SLA bits in I2CSAR...

Page 148: ...o ACK signal is detected and master transmits repeated START condition In this case load SLA R W into the I2CDR and set the STARTC bit in I2CCR After doing one of the actions above clear to 0b all int...

Page 149: ...Else if the address equals to SLA bits and the ACKEN bit is enabled I2C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN bit is dis...

Page 150: ...equals to SLA bits and the ACKEN bit is enabled I2C generates SSEL interrupt and the SCL line is held LOW Note that even if the address equals to SLA bits when the ACKEN bit is disabled I2C enters id...

Page 151: ...W 00H I2C Data Register I2CSDHR EDH R W 01H I2C SDA Hold Time Register I2CSCLR EEH R W 3FH I2C SCL Low Period Register I2CSCHR EFH R W 3FH I2C SCL High Period Register Table 11 13 I2C Register Map 11...

Page 152: ...ure this register regarding the frequency of SCL from master The SDA is changed after tsclk X I2CSDHR 2 in master mode So to insure operation in slave mode the value tSCLK X I2CSDHR 2 must be smaller...

Page 153: ...her I2C allows general call address or not in I2C slave mode 0 Ignore general call address 1 Allow general call address I2CSAR1 I2C Slave Address 1 Register F1H 7 6 5 4 3 2 1 0 I2CSLA16 I2CSLA15 I2CSL...

Page 154: ...Controls ACK signal Generation at ninth SCL period 0 No ACK signal is generated SDA 1 1 ACK signal is generated SDA 0 NOTE ACK signal is output SDA 0 for the following 3 cases 1 When received address...

Page 155: ...n is detected 1 STOP condition is detected SSEL NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a slave MLOST...

Page 156: ...f the functional safety standards they offer a means of verifying the Flash memory integrity The CRC generator helps compute a signature of the software during runtime to be compared with a reference...

Page 157: ...et FCSARH 0x00 FCSARM 0x00 FCSARL 0x00 CRC end address set FCEARH 0x00 FCEARM 0x3F FCEARL 0xFF CRC start FCCR _0000_0001 _nop_ Dummy instruction This instruction must be needed _nop_ Dummy instruction...

Page 158: ...ROM 4 Write the data to FCDIN Register 5 Read the CRC result Program Tip User CRC Checksum mode unsigned char code rom_addr 0x0000 unsigned int i 0 FCCR _1000_0000 Flash CRC User CRC Checksum Mode FCC...

Page 159: ...rt address set FCSARH 0x00 FCSARM 0x00 FCSARL 0x00 Checksum end address set FCEARH 0x00 FCEARM 0x3F FCEARL 0xFF Checksum start FCCR _0000_0001 _nop_ Dummy instruction This instruction must be needed _...

Page 160: ...ROM 4 Write the data to FCDIN Register 5 Read the Checksum result Program Tip User CRC Checksum mode unsigned char code rom_addr 0x0000 unsigned int i 0 FCCR _1000_0000 Flash CRC User CRC Checksum Mod...

Page 161: ...m 11 10 2 Register Map Name Address Direction Default Description FCSARH 5050H XSFR R W 00H Flash CRC Start Address High Register FCEARH 5051H XSFR R W 00H Flash CRC End Address High Register FCSARM 5...

Page 162: ...rt Address High Register 5050H 7 6 5 4 3 2 1 0 FCSARH0 R W Initial value 00H FCSARH0 Flash CRC Start Address High NOTE 1 Used only to Auto CRC Mode FCSARM Flash CRC Start Address Middle Register 5052H...

Page 163: ...1 Used only to Auto CRC Mode FCEARL Flash CRC End Address Low Register 5055H 7 6 5 4 3 2 1 0 FCEARL7 FCEARL6 FCEARL5 FCEARL4 FCEARL3 FCEARL2 FCEARL1 FCEARL0 R W R W R W R W R W R W R W R W Initial val...

Page 164: ...sed only to User CRC Mode MDSEL CRC Checksum Selection 0 Select CRC 1 Select Checksum CKSEL 2 0 Select Flash CRC Clock CKSEL2 CKSEL1 CKSEL0 Description 0 0 0 fHFIRC 0 0 1 fHFIRC 2 0 1 0 fHFIRC 4 0 1 1...

Page 165: ...tch Timer Operates Continuously Stop Can be operated with sub clock Timer0 2 Operates Continuously Halted Only when the Event Counter Mode is Enabled Timer operates Normally ADC Operates Continuously...

Page 166: ...and peripherals are operated normally but CPU stops It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because the device bec...

Page 167: ...ock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabilization time is required to nor...

Page 168: ...e STOP mode is released by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is released...

Page 169: ...r 87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTE 1 To enter...

Page 170: ...rs Table 13 1 Reset State 13 2 Reset Source The MC96F8204 has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN...

Page 171: ...power the POR Power On Reset has a function to reset the device If POR is used it executes the device RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fast VDD Rising Time Figu...

Page 172: ...igure Read POR VDD Input Internal OSC VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h...

Page 173: ...oltage for Config read Slew Rate 0 05V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR or Ext_reset release...

Page 174: ...te the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diagram after RESET F...

Page 175: ...0V 2 65V 2 82V 3 01V 3 22V 3 47V 3 76V 4 10V 4 51V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN bit is set to o...

Page 176: ...g when BOD RESET VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h about 16ms F1 00 01...

Page 177: ...egister Map Name Address Direction Default Description RSTFR E8H R W 80H Reset Flag Register LVRCR D8H R W 00H Low Voltage Reset Control Register LVICR 86H R W 00H Low Voltage Indicator Control Regist...

Page 178: ...n OCDRF On Chip Debug Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection LVRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit...

Page 179: ...this bit is 0 the LVREN bit is not effect by stop mode release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 60V 0 0 0 1 2 05V 0 0 1 0 2 15V 0 0 1 1 2 25V 0 1 0 0 2 37...

Page 180: ...H LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2 05V 0 0 0 1 2...

Page 181: ...n On chip debug system OCD of MC96F8204 can be used for programming the non volatile memories and on chip debugging Detail descriptions for programming via the OCD interface can be found in the follow...

Page 182: ...Including Break Instruction Single Step Break Program Memory Break Points on Single Address Programming of Flash EEPROM Fuses and Lock Bits through the two wire Interface On chip Debugging Supported b...

Page 183: ...bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge...

Page 184: ...3 Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus data line stable data valid except Start and Stop change of data allowed DSDA DSCL St Sp START STOP DSD...

Page 185: ...cedure Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1 TSCLK for next byte transmission Acknowled...

Page 186: ...directional I O Figure 14 8 Connection of Transmission DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave...

Page 187: ...sed and overwritten while mounted on the board The flash memory can be read by MOVC instruction and it can be programmed in OCD serial ISP mode or user program mode Flash Size 4Kbytes Single power sup...

Page 188: ...FC0H 00FBFH 00FA0H Sector 125 00FA0H 00F9FH Sector 124 Sector 2 00040H 0003FH 00020H Sector 1 00020H 0001FH 00000H Sector 0 00000H 00040H 8000H Flash Page Buffer External Data Memory 32bytes 801FH ROM...

Page 189: ...ash Identification Register FMCR FEH R W 00H Flash Mode Control Register Table 15 1 Flash Memory Register Map 15 1 4 Register Description for Flash Memory Control and Status Flash control register con...

Page 190: ...7 0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R W R W R W R W R W R W Initial va...

Page 191: ...nterrupt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 32bytes to 0 0 1 0 S...

Page 192: ...s are available only when the PAEN bit is cleared to 0 that is enable protection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can be used as a n...

Page 193: ...instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_clr MOVX DPTR A INC DPTR DJNZ R0 Pgbuf_clr Write...

Page 194: ...nstruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_WR MOVX DPTR A...

Page 195: ...ion This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buffer MOV A 6 MOV DPH 0x80 MOV DPL 0x05 MOVX DP...

Page 196: ...riteErase MOV A ID_DATA_2 CJNE A UserID2 No_WriteErase MOV A ID_DATA_3 CJNE A UserID3 No_WriteErase MOV FMCR 0x 0x03 if write 0x02 if erase RET No_WriteErase MOV FIDR 00H MOV UserID1 00H MOV UserID2 0...

Page 197: ...ork2 CALL ID_write CALL Work3 CALL Flash_erase CALL Flash_write ID_wire MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV UserID1 ID_DATA_1 Write Uiser ID1 MOV A 38...

Page 198: ...ase for flash memory to be erased by malfunction noise and power off Figure 15 2 Flow of Protection for Invalid Erase Write Start Work1 Set Flags Write UserID1 2 3 Clear the Flag Clear UserID1 2 3 Wri...

Page 199: ...k the UserID for to prevent the invalid work Note 3 Set flash mode control register FMCR NOTE Please refer to the chapter Protection for Invalid Erase Write Program Tip Code Write Protection MOV FIDR...

Page 200: ...Protection 0 Disable Protection Erasable by instruction 1 Enable Protection Not erasable by instruction RSTS Select RESETB pin 0 Disable RESETB pin P05 1 Enable RESETB pin CONFIGURE OPTION 2 ROM Addre...

Page 201: ...t byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A d...

Page 202: ...1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR d...

Page 203: ...DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 E0 MOVX Ri...

Page 204: ...mpare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct byte...

Page 205: ...he flags in program and check the flags in main loop at the end When the Flash Erase Write is executed check the flags If not matched do not execute Check the range of Flash Sector Address If the flas...

Page 206: ...rite Flash Set User_ID1 Working Check User_ID1 Set User_ID2 Working Check User_ID2 Set User_ID3 Working Yes Yes Yes No No No Write Flash Clear User_ID1 2 3 Clear FIDR Clear FMCR Set FSADRH M L to Dumm...

Page 207: ...e Write in flash Set to Dummy address after Erase Write Even if invalid work occurred it will be Erase Write in Dummy address in flash Check Flags If every flag User_ID1 2 3 LVI Flash Address Min Max...

Page 208: ...High Frequency Internal RC Oscillator Characteristics 25 7 7 Low Frequency Internal RC Oscillator Characteristics 25 7 8 Internal Watch Dog Timer RC Oscillator Characteristics 25 7 9 DC Characteristic...

Page 209: ...73 10 7 Multi Interrupt 74 10 8 Interrupt Enable Accept Timing 75 10 9 Interrupt Service Routine Address 75 10 10 Saving Restore General Purpose Registers 75 10 11 Interrupt Timing 76 10 12 Interrupt...

Page 210: ...er 113 11 7 1 Overview 113 11 7 2 Conversion Timing 113 11 7 3 Block Diagram 114 11 7 4 ADC Operation 115 11 7 5 Register Map 117 11 7 6 ADC Register Description 117 11 7 7 Register Description for AD...

Page 211: ...68 12 6 Register Map 169 12 7 Power Down Operation Register Description 169 12 8 Register Description for Power Down Operation 169 13 RESET 170 13 1 Overview 170 13 2 Reset Source 170 13 3 RESET Block...

Page 212: ...8 Erase Mode 193 15 1 9 Write Mode 194 15 1 10 Protection for Invalid Erase Write 196 15 1 10 1 Flow of Protection for Invalid Erase Write 198 15 1 11 Read Mode 199 15 1 12 Code Write Protection Mode...

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