184
MC96F8204
ABOV Semiconductor Co., Ltd.
14.2.2 Packet Transmission Timing
14.2.2.1
Data Transfer
Figure 14.3
Data Transfer on the Twin Bus
14.2.2.2
Bit Transfer
Figure 14.4
Bit Transfer on the Serial Bus
data line
stable:
data valid
except Start and Stop
change
of data
allowed
DSDA
DSCL
St
Sp
START
STOP
DSDA
DSCL
LSB
acknowledgement
signal from receiver
ACK
ACK
1
10
1
10
acknowledgement
signal from receiver
LSB
Summary of Contents for MC96F8204 Series
Page 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...
Page 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...
Page 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...
Page 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...
Page 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...
