73
MC96F8204
ABOV Semiconductor Co., Ltd.
10.6 Effective Timing after Controlling Interrupt Bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Figure 10.4
Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Figure 10.5
Effective Timing of Interrupt Flag Register
Interrupt Flag Register
Command
Next Instruction
Next Instruction
After executing next instruction,
interrupt flag result is effective.
Interrupt Enable Register
command
Next Instruction
Next Instruction
After executing IE set/clear, enable
register is effective.
Summary of Contents for MC96F8204 Series
Page 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...
Page 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...
Page 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...
Page 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...
Page 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...
