Abov MC96F8104M, User Manual, Page: 94 / 212

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MC96F8204 ABOV Semiconductor Co., Ltd.
11.4.3 Register Map
Name Address Direction Default Description
WTCNT 9FH R 00H Watch Timer Counter Register
WTDR 9FH W 7FH Watch Timer Data Register
WTCR 9EH R/W 00H Watch Timer Control Register
Table 11.4
Watch Timer Register Map
11.4.4 Watch Timer Register Description
The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR) and
watch timer control register (WTCR). As WTCR is 6-bit writable/readable register, WTCR can control the clock source
(WTCK[1:0]), interrupt interval (WTIN[1:0]) and function enable/disable (WTEN). Also there is WT interrupt flag bit
(WTIFR).
11.4.5 Register Description for Watch Timer
WTCNT (Watch Timer Counter Register: Read Case): 9FH
7 6 5 4 3 2 1 0
–
WTCNT 6 WTCNT 5 WTCNT 4 WTCNT 3 WTCNT 2 WTCNT 1 WTCNT0
–
R R R R R R R
Initial value: 00H
WTCNT[6:0] WT Counter
WTDR (Watch Timer Data Register: Write Case): 9FH
7 6 5 4 3 2 1 0
WTCL WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0
R/W W W W W W W W
Initial value: 7FH
WTCL Clear WT Counter
0 Free Run
1 Clear WT Counter (auto clear after 1 Cycle)
WTDR[6:0] Set WT period
WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1))
NOTE)
1. Do not write
“0” in the WTDR register.