Abov MC96F8104M, User Manual, Page: 82 / 212

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MC96F8204 ABOV Semiconductor Co., Ltd.
EIFLAG (External Interrupt Flag 0 Register) : C0H
7 6 5 4 3 2 1 0
–
T0IFR IICIFR FLAG12 FLAG11 FLAG10 FLAG1 FLAG0
–
R/W R/W R/W R/W R/W R/W R/W
Initial value : 00H
T0IFR When T0 interrupt occurs, this bit becomes
‘1’. For clearing bit, write ‘0’ to this bit or
auto clear by INT_ACK signal. Writing
“1” has no effect.
0 T0 interrupt no generation
1 T0 interrupt generation
IICIFR This is an interrupt flag bit. When an interrupt occurs, this bit becomes
‘1’. This bit is
cleared when all interrupt source bits in the I2CSR register are cleared to
“0b”. Writing
“1” has no effect.
0 I2C interrupt no generation
1 I2C interrupt generation
EIFLAG[4:0] When an external interrupt (EINT0/1/10/11/12) is occurred, the flag becomes
‘1’. The
flag is cleared by writing a
‘0’ to the bit or automatically cleared by INT_ACK signal.
Writing
“1” has no effect.
0 External Interrupt 0/1/10/11/12 not occurred
1 External Interrupt 0/1/10/11/12 occurred
EIPOL0 (External Interrupt Polarity 0 Register): A4H
7 6 5 4 3 2 1 0
– – – –
POL1 POL0
– – – –
R/W R/W R/W R/W
Initial value: 00H
EIPOL0[3:0] External interrupt (EINT0,EINT1) polarity selection
POLn[1:0] Description
0 0 No interrupt at any edge
0 1 Interrupt on rising edge
1 0 Interrupt on falling edge
1 1 Interrupt on both of rising and falling edge
Where n = 0 and 1
EIPOL1 (External Interrupt Polarity 1 Register): A5H
7 6 5 4 3 2 1 0
– –
POL12 POL11 POL10
– –
R/W R/W R/W R/W R/W R/W
Initial value: 00H
EIPOL1[5:0] External interrupt (EINT10,EINT11,EINT12) polarity selection
POLn[1:0] Description
0 0 No interrupt at any edge
0 1 Interrupt on rising edge
1 0 Interrupt on falling edge
1 1 Interrupt on both of rising and falling edge
Where n = 10, 11, and 12