129
MC96F8204
ABOV Semiconductor Co., Ltd.
11.8.9.5
Asynchronous Data Reception
To receive asynchronous data frame, the USART includes a clock and data recovery unit. Theclock recovery logic is
used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD
pin.
The data recovery logic does sampling and low pass filtering the incoming bits, and removing the noise of RXD pin.
The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of
the baud-rate in normal mode and 8 times the baud-rate for double speed mode (DBLS=1). The horizontal arrows
show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is
shown when using the double speed mode.
Figure 11.29
Asynchronous Start Bit Sampling
RXD
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
IDLE
BIT0
START
0
1
2
3
4
5
6
7
8
1
2
Sample
(DBLS = 0)
Sample
(DBLS = 1)
Summary of Contents for MC96F8104M
Page 13: ...13 MC96F8204 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 20 Pin SOP Package...
Page 14: ...14 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 2 20 Pin TSSOP Package...
Page 15: ...15 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 3 16 Pin SOPN Package...
Page 16: ...16 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 4 10 Pin SSOP Package...
Page 17: ...17 MC96F8204 ABOV Semiconductor Co Ltd Figure 4 5 8 Pin SOP Package...