MC80F0304/08/16
November 4, 2011 Ver 2.12
103
.
Figure 19-2 SLEEP Mode Release Timing by External Interrupt
Figure 19-3 Timing of SLEEP Mode Release by Reset
19.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripher-
al clock is stopped, but RC-oscillated watchdog timer continue to
operate. With the clock frozen, all functions are stopped, but the
on-chip RAM and Control registers are held. The port pins out the
values held by their respective port data register, port direction
registers. Oscillator stops and the systems internal operations are
all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
"STOP" which starts the STOP operating mode.
Note:
The Stop mode is activated by execution of STOP instruc-
tion after setting the SSCR to “5A
H
”. (This register should be writ-
ten by byte operation. If this register is set by bit manipulation
instruction, for example "set1" or "clr1" instruction, it may be undes-
ired operation)
In the Stop mode of operation, V
DD
can be reduced to minimize
power consumption. Care must be taken, however, to ensure that
V
DD
is not reduced before the Stop mode is invoked, and that
V
DD
is restored to its normal operating level, before the Stop
mode is terminated.
The reset should not be activated before V
DD
is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
Oscillator
(X
IN
pin)
~~
Normal Operation
SLEEP Operation
~~
~~
~~
~~
External Interrupt
Internal Clock
SLEEP Instruction
Executed
~~
Normal Operation
~~
~~
~~
SLEEP Instruction
Stabilization Time
t
ST
= 65.5mS @4MHz
Internal
~~
~~
~~
RESET
RESET
Oscillator
(X
IN
pin)
~~
CPU
Clock
~~
~~
Execution
Normal Operation
SLEEP Operation
Normal Operation
