Abit WB6, User Manual

Page: 52 / 118

3-20 Chapter3
WB6
SDRAM Cycle Time Tras/Trc:
Two options are available: 5/7 and 6/8. The default setting is 6/8 . This item controls the
number of SDRAM clocks (SCLKs) used per access cycle.
SDRAM RAS-to-CAS Delay
Two options are available: 2 and 3. The default setting is 3 . This item lets you insert a timing
delay between the CAS and RAS strobe signals, used when DRAM is written to, read from,
or refreshed. Fast gives faster performance; and Slow gives more stable performance. This
item applies only when synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time:
Two options are available: 2 and 3. The default setting is 3 . This option lets you insert a
timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read
from, or refreshed. Fast gives faster performance; and Slow gives more stable performance.
This item applies only when synchronous DRAM is installed in the system.
System BIOS Cacheable:
You can select Enabled or Disabled. The default setting is Enabled . When you select
Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better
system performance. However, if any program writes to this memory area, a system error
may result.
Video BIOS Cacheable:
You can select Enabled or Disabled. The default setting is Enabled . When you select
Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result.
Memory Hole At 15M-16M:
Two options are available: Enabled and Disabled. The default setting is Disabled . This
option is used to reserve the memory block 15M-16M for ISA adapter ROM. Some special
peripherals need to use a memory block located between 15M and 16M, and this memory
block has a size of 1M. We recommend that you disable this option.