Abit KW7-G, User Manual

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3-14 Chapter 3
AGP Master 1 WS Write:
Two options are available: Disabled Enabled. The default setting is Disabled . This implements a
single delay when writing to the AGP Bus. When you set it to Enabled , two-wait states are used by the
system, allowing for greater stability.
AGP Master 1 WS Read:
Two options are available: Disabled Enabled. The default setting is Disabled . This implements a
single delay when reading to the AGP Bus. When you set it to Enabled , two-wait states are used by the
system, allowing for greater stability.
AGP 3.0 Calibration cycle:
This item controls the time cycle between AGP and North Bridge. You may try the [Enabled] option if
problems occurred when using some graphics cards of AGP 3.0 specifications.
NOTE:
This item appears only when installing graphics card of AGP 3.0 specifications.
Back to Advanced Chipset Features Setup Menu:
CPU & PCI Bus Control:
Click <Enter> key to enter its submenu:
Phoenix – AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI Master 0 WS Write [Enabled] Item Help
CPU to PCI Post Write [Enabled]
VLink 8x Support [Enabled]
PCI Delay Transaction [Disabled]
↑↓
:Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
PCI Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled . When Enabled, writes to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to
Disabled , the system will wait one state before data is written to the PCI bus.
KW7 Series