BIOS Setup
3-11
DRAM ECC Mode:
When set to [ECC], your DRAM module will support the ECC Mode.
CAS Latency Time:
Three options are available: 2
2.5
3. The default setting is
2.5
. You can select SDRAM CAS
(
C
olumn
A
ddress
S
trobe) latency time according your SDRAM specification.
Row Cycle Time:
This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank.
Row Refresh Cycle Time:
This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time.
RAS# to CAS# Delay:
This item specifies the RAS# active to CAS# read write delay time to the same bank.
RAS# to RAS# Delay:
This item specifies the RAS# active to RAS# active delay time of different bank.
Min. RAS# Active Time:
This item specifies the minimum RAS# active time.
RAS# Precharge Time:
This item specifies the RAS# precharge time.
Write Recovery Time:
This item specifies the time measured from the last write datum is safely registered by the DRAM.
Write to Read Delay:
This item specifies the time measured from the rising edge following the last non-masked data strobe to
the rising edge of the next read command.
Read to Write Delay:
This item specifies the read to write delay.
DRAM Command Rate:
This item specifies the DRAM command rate.
User’s Manual
Summary of Contents for KV8
Page 1: ...KV8 KV8 MAX3 AMD AthlonTM 64 System Board Socket 754 User s Manual 4200 0410 01 Rev 1 00 ...
Page 7: ...Introduction 1 3 1 2 Layout Diagram User s Manual ...
Page 8: ...1 4 Chapter 1 KV8 KV8 MAX3 ...
Page 54: ...B 2 Appendix B B 2 Appendix B KV8 KV8 MAX3 KV8 KV8 MAX3 ...
Page 56: ...C 2 Appendix C C 2 Appendix C KV8 KV8 MAX3 KV8 KV8 MAX3 ...
Page 58: ...D 2 Appendix D Click Yes 6 Click OK 7 Click Print to File 8 Click OK 9 KV8 KV8 MAX3 ...
Page 66: ...G 2 Appendix G KV8 KV8 MAX3 ...
Page 72: ...H 6 Appendix H KV8 KV8 MAX3 ...
