Publication No: 500-9300007768-000 Rev. H.0
Embedded PC/RTOS Features 53
3.3.9 Timer 1 IRQ Clear (T1IC)
The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by
Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2,
causes the interrupt from Timer 1 to be cleared. This can also be done by writing a
“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.
3.3.10 Timer 2 IRQ Clear (T2IC)
The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by
Timer 2. Writing to this register, located at offset 0x34 from the address in BAR2,
causes the interrupt from Timer 2 to be cleared. This can also be done by writing a
“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.
3.3.11 Timer 3 IRQ Clear (T3IC)
The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by
Timer 3. Writing to this register, located at offset 0x38 from the address in BAR2,
causes the interrupt from Timer 3 to be cleared. This can also be done by writing a
“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.
3.3.12 Timer 4 IRQ Clear (T4IC)
The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by
Timer 4. Writing to this register, located at offset 0x3C from the address in BAR2,
causes the interrupt from Timer 4 to be cleared. This can also be done by writing a
“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status
Register (TCSR1). This register is write only and the data written is irrelevant.
3.4 Watchdog Timer
The “WDT Timeout Select” field is used to select the timeout value of the WDT
as shown in
The V7768/V7769 provide a programmable Watchdog Timer (WDT) which can be
used to reset the system if software integrity fails.
3.4.1 WDT Control Status Register (WCSR)
The WDT is controlled and monitored by the WDT Control Status Register
(WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of
the bits in this register is shown in
Table 3-11 WCSR Bit Mapping
Field
Bits
Read or Write
SERR/RST Select
WCSR[16]
R/W
WDT Timeout Select WCSR[10..8]
R/W
WDT Enable
WCSR[0]
R/W
All of these bits default to “0” after system reset. All other bits are reserved.
