20 PEX430
Publication No. PEX430-0HH/1QD
4.1.2
VPX PCI Express Port
The PEX430 has a PCI Express (PCIe) connection to the VPX connectors. This
interface can be configured in a number of different ways as described in the table
below. One of these ports in each case will be configured as the upstream port. One
of these ports in each case can be configured as a Non-Transparent port. This allows
the memory spaces of two connected systems to remain isolated by presenting the
processor as an end point. If one of these ports is configured as a non-transparent
port then there can be either a single upstream port or two upstream ports (one
transparent port and one non-transparent).
Table 4-1
Port 0
Port 1
Port 2
Port 3
x16 lane
x0 lane
x0 lane
x0 lane
x8 lane
x8 lane
x0 lane
x0 lane
x8 lane
x4 lane
x4 lane
x0 lane
x8 lane
x4 lane
x2 lane
x2 lane
x4 lane
x4 lane
x4 lane
x4 lane
Ports can be configured as transparent or non transparent in the following
combinations:
Single transparent port
Single non transparent port
Single transparent port and single non transparent port
By default the PEX430 is configured as 4 ports each with 4 lanes with Port 0 as a
transparent port. The setting of the PEX430 with a non-transparent port requires the
use of configuration data stored in the associated EEPROM.
For a PEX430 set up for x4 x4 x4 x4 lane operation Port 0 corresponds to the 4 lanes
described as Channel A. For a PEX430 set up for x8 x8 x0 x0 or x8 x4 x4 x0 or x8 x4 x2
x2 Port 0 corresponds to the 8 lanes described as Channel A and Channel B
combined.
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