Aaeon SBC-656, User Manual

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66 SBC-656 User Manual
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user informa-
tion of peripherals that need to use this area of system memory
usually discusses their memory requirements.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another PCI
master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance
with PCI specification version 2.1.
Auto Detect DIMM/PCI Clk
When the Auto Detect DIMM/PCI clk enable, the Utility will
automatically detect the DIMM/PCI clock in your system.
Spread Spectrum
When the system clock generator pulses, the extreme values of the
pulse generate excess EMI. Enabling pulse spectrum spread
modulation changes the extreme values from spikes to flat curves,
thus reducing EMI. This benefit may in some cases be outweighed
by problems with timing-critical devices, such as a clock-sensitive
SCSI device
IN0-IN6(V)
These fields display the current voltage of up to seven voltage
input lines, if your computer contains a monitoring system.