Aaeon SBC-656, User Manual

Page: 75 / 120

Chapter 3 Award BIOS Setup 65
SDRAM Precharge Control
When Enabled, all CPU cycles to SDRAM result in an All Banks
Precharge Command on the SDRAM interface.
DRAM Data Integrity Mode
Select Non-ECC or ECC (error-correcting code), according to the
type of installed DRAM.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However,
if any program writes to this memory area, a system error may
result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at
C0000h to C7FFFh, resulting in better video performance. However,
if any program writes to this memory area, a system error may
result.
Video RAM Cacheable
Selecting Enabled allows caching of the video memory (RAM) at
A0000h to AFFFFh, resulting in better video performance. Howev-
er, if any program writes to this memory area, a memory access error
may result.
8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for
16-bit and 8-bit I/O.