Aaeon PCM-5892, Manual

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58 PCM-5894/5892 User Manual
Auto Configuration
Set this item to Enabled to pre-defined values for DRAM, cache
timing according to CPU type & system clock. Thus, each item
value may display differently depending on your system configura-
tions.
When this item is enabled, the pre-defined items will become
SHOW-ONLY.
Esc:Quit
áâàß
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Auto Configuration : Enabled
L2 (WB) Tag Bit Length : 8bits
SRAM Back-to-BACK : Disabled
NA# Enable : Disabled
Starting Point of Paging : 1T
Refresh Cycle Time (us) : 187.2
RAS Pulse Width Refresh
: 6T
RAS Precharge Time : 4T
RAS to CAS Delay : 4T
CAS# Pulse Width (FP) : 2T
CAS# Pulse Width (EDO) : 1T
RAMW# Assertion Timing : 3T
CAS Precharge Time (FP) : 1T/2T
CAS Precharge Time (EDO) : 1T/2T
Enhanced Memory Write
: Disabled
Read Prefetch Memory RD : Disabled
CPU to PCI Post Write
: 3T
CPU to PCI Burst Mem.WR: Disabled
ISA Bus Clock Frequency
: PCICLK/4
CHIPSET features setup
System BIOS Cacheable : Enabled
Video BIOS Cacheable : Enabled
Memory Hole at 15M-16M : Disabled
Boot ROM Function : Disabled
R O M P C I / I S A B I O S ( 2 A 5 I I A K 9 )
C H I P S E T F E A T U R E S S E T U P
A W A R D S O F T W A R E , I N C .