Aaeon PCM-4330, Instructions Manual

Page: 69 / 127

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DMA Channels
The PCM-4330 single board computer provides a total of seven DMA channels.
Two 82c37-compatible DMA controllers in the SIS-85C471-AT-Controller are AT-
compatibly cascaded as MASTER and SLAVE.
DMA Channel Assignment
Channel 0 of the Master-Controller (= DMA channel 4) is used to cascade input for
the Slave-Controller.
Channels 0 to 3 (Slave) support 8-bit DMA data transfer between an 8-bit I/O unit
and the 8/16-bit main memory. Channels 5 to 7 (Master 1 to 3) support 16-bit DMA
data transfer between a 16-bit I/O component and the 16-bit main memory.
Channels 5 to 7 can only address data on even byte boundaries.
DMA Address Generation
The limited addressing capability (16 address lines = 64 kB memory) of the 8237-
DMA controller is extended to 16 MB by the Low-Page-Registers.
The address is constituted by the contents of the Low-Page-Register and the DMA
controller address in the current address register.
Port A
The SIS-85C471-AT-Controller. supports port A (I/O address 92h) of the PS/2 ®
system family. This offers a fast alternative to the PC/AT standard for controlling
CPU resets and A20 control.
Port 92h Data Port Description
PS/2 RES RES RES RES RES RES A20 RST
x x x x x x r/w r/w
D7 D6 D5 D4 D3 D2 D1 D0
5.3
Bit Name Function
7- 2 RES Reserved bits, always read “1”
1 A20 Fast A20 shift
0
= A20-line always low
1 = A20 under CPU control
0 RST Fast CPU reset
0
= no reset initiated
1 = initiate reset
5.3.1
5.3.2
5.4