Aaeon Gene-6320, Manual

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50 GENE-6320 User Manual
EDO CASx# MA Wait State
We may elect to insert one additional wait state before the asser-
tion of the first CASx# for page hit cycles, thus allowing one
additional clock of MA setup time to the CASx# for the leadoff
page hit cycle. Do not change the default unless you are getting
memory addressing errors. This field applies only if EDO DRAM is
installed in the system.
The choices: 1, 2.
EDO RASx# Wait State
We may elect to insert one additional wait state before RAS# is
asserted for row misses, thus allowing one additional MAX[13:0]
setup time to RASx# assertion. This field applies only if EDO
DRAM is installed in the system.
The choices: 1, 2.
SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS and RAS
strobe signals, used when DRAM is written to, read from, or
refreshed. This field applies only when synchronous DRAM is
installed in the system.
The choices: 3, 2.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. This field applies
only when synchronous DRAM is installed in the system.
The choices: 3, 2.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles
of CAS latency depends on the DRAM timing. Do not reset this
field from the default value specified by the system designer.
The choices: 3, 2.