User Manual
UM015201-0603
Peripheral Bus Connector
ZiLOG Development Platforms
eZ80
®
Sales Demonstration Platform
10
IOREQ
Bidirectional
Bus Cycle I/O indication.
RD
Bidirectional
Bus Cycle read indication.
WR
Bidirectional
Bus Cycle write indication.
INSTRD
n/a
IN
Bus Cycle Instruction read indication
BUSACK
IN
Bus Acknowledge output
BUSREQ
Pull-Up 10k OUT
Bus Request input
V
CC
n/a
n/a
3.3 V Supply Input Pin
GND
n/a
n/a
V
SS
/Ground (0V)
Table 2. Peripheral Bus Connector Pin Identification (see Figure 5 for Pin #s)
Function
Pull
Up/Down*
Signal Direction
(with respect to
the Platform
board)
Description
Notes: *External capacitive loads on RD, WR, IOREQ, MREQ, D0–D7 and A0–A23 must be below 10pF to
satisfy timing requirements for the eZ80® CPU. All unused inputs must be pulled to either V
DD
or
GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated by software in the eZ80F92 Peripheral
Power-Down Register. All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.
