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4. IDE INTERFACE

The Integrated Drive Electronics (IDE) Interface is composed of 10 register locations in
the I/O map. This chapter describes the common registers used by all manufacturers.

Many manufacturers have added superset commands for such things as diagnostic
utilities and power down modes for low power applications. Consult Ziatech for specific
drive commands or features.

IDE INTERFACE REGISTERS

Data Register

(1F0h, Read/Write - 8 or 16 bits)

All data transferred between the hard disk and the host CPU passes through the data
register. The host CPU passes sector table information during execution of the
FORMAT command. ZT 8952's control circuitry dynamically packs and unpacks 16-bit
data for 8-bit processors. In 16-bit systems, full 16-bit transfers are performed.

Transfers of ECC bytes are 8-bit transfers during the execution of the Read/Write Long
command.

Error Register

(1F1h, Read - 8 bits)

The error register contains status information about the last command executed by the
drive. The contents of this register are valid only when the error bit (ER) is set in the
status register, except after power-on or after the completion of an internal diagnostic.
Error bits are defined in the "Error Register" figure following.

7

6

5

4

3

2

1

0

ID Field Not Found

Aborted Command

Track 0 Not Found

ABRT TK0

IDNF

-

UNC

BBK

Uncorrected Data Error

Bad Block

-

-

Error Register

Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

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Содержание ZT 8952

Страница 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Страница 2: ...Integrated Drive Electronics IDE Interfaces ZT 8952 ZT 8953 Hardware User Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 3: ...16 I O 17 INTERRUPTS 18 DIRECT MEMORY ACCESS DMA 18 IDE REGISTERS 19 4 IDE INTERFACE 20 IDE INTERFACE REGISTERS 20 DATA REGISTER 20 ERROR REGISTER 20 WRITE PRECOMPENSATION REGISTER 21 SECTOR COUNT RE...

Страница 4: ...REQUIREMENTS 51 STD BUS LOADING CHARACTERISTICS 51 MECHANICAL 54 CARD DIMENSIONS AND WEIGHT 54 CONNECTORS 54 C GLOSSARY 59 COMMAND CODES 59 TERMINOLOGY 60 D CUSTOMER SUPPORT 62 TECHNICAL SALES ASSIST...

Страница 5: ...using the ZT 8952 Chapter 3 Operational Overview presents answers to some frequently asked questions and a detailed description of the ZT 8952 interface to STD 32 bus structures Other topics discussed...

Страница 6: ...Both 8 bit and 16 bit transfers are supported under STD 32 The ZT 8952 will support up to four Mbytes second transfer rates on the backplane one word every four 8 MHz cycles The actual transfer rate w...

Страница 7: ...E Hard Disk Either a 2 inch drive ZT 8952 or a 3 inch drive may be mounted directly to the interface to provide a compact modular unit for STD applications The drive may also be remotely mounted and c...

Страница 8: ...INTRQ2 CNTRL INTRQ3 or IRQx on the backplane Alternatively one of five frontplane interrupts may be selected to provide interrupt support 2 1 2 in or 3 1 2 in IDE Hard Disk Bus Interface Logic Interr...

Страница 9: ...MOS devices the ZT 8952 must be protected from static discharge Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the ZT 8952 to handle t...

Страница 10: ...ion requirements The following jumper configurations are suggested These configurations will vary depending upon the application 16 Bit Vs 8 Bit STD 32 Transfers Jumper W2 controls whether or not the...

Страница 11: ...errupt W5 is loaded to select FP5 but some versions of STD DOS will use alternative selections If you need an interrupt remove the jumper from W5 and use it to select the desired interrupt The ZT 8902...

Страница 12: ...s the following STD 32 compliance I O Slave SA16 SA8 I IXL IXP Definitions SA16 STD 80 style 16 bit transfers SA8 STD 80 style 8 bit transfers I Drives INTRQ INTRQ1 INTRQ2 CNTRL INTRQ3 IXL Drives IRQx...

Страница 13: ...cal media This logic improves performance by relieving an external controller s need to manage the physical media While the AT style IDE drive is the most popular interface other drives are available...

Страница 14: ...r style 2 mm cable used to cable to a remote drive via a 1 mm ribbon cable 2 inch drives use the 2 mm connector The connector used depends upon the connector type used by the drive Ziatech BIOS versio...

Страница 15: ...tion Drive H Fixed Disk 1 Extended Partition Drive I Fixed Disk 1 Extended Partition Drive J Fixed Disk 1 Extended Partition Drive C is assigned to the primary partition in a single drive system The F...

Страница 16: ...igurations for a two drive system In general a higher capacity drive is more cost effective than two drives in a master slave arrangement A single drive will generally require less power and have a be...

Страница 17: ...h which causes the ZT 8952 to drive the signal IO16 low This informs the CPU that a 16 bit transfer is desired If the CPU is a 16 bit processor such as the ZT 8901 and the system is an STD 32 system t...

Страница 18: ...s 3F6h 3F7h Note that use with the ZT 8950 Floppy Disk Controller requires that the ZT 8950 be Revision A 2 or greater This is because both the ZT 8952 8953 and the ZT 8950 share register 3F7h HCS1 HC...

Страница 19: ...ow illustrates the possible interrupt selections ZT 8902 and ZT 8911 systems should have W15 installed Interrupt Logic W7 W6 W5 W4 W3 2 FP1 4 FP3 6 FP5 8 FP6 10 FP7 J 3 W11 W12 W13 W14 E47 P37 P44 P50...

Страница 20: ...UNCTION 1F0h Data Register Data Register 1F1h Error Register Write Precompensation Reg 1F2h Sector Count Sector Count 1F3h Sector Number Sector Number 1F4h Cylinder Low Cylinder Low 1F5h Cylinder High...

Страница 21: ...ZT 8952 s control circuitry dynamically packs and unpacks 16 bit data for 8 bit processors In 16 bit systems full 16 bit transfers are performed Transfers of ECC bytes are 8 bit transfers during the e...

Страница 22: ...write precompensation is typically not used Most IDE drives do not require write precompensation Some drives define an alternate usage for this register Sector Count Register 1F2h Read Write 8 bits T...

Страница 23: ...ster contains the low order 8 bits of the starting cylinder address for any disk access On multiple sector transfers that cross cylinder boundaries the host updates this register when the command is e...

Страница 24: ...ntly selected head Register bits are defined in the following figure SDH Register 7 6 5 4 3 2 1 0 Drive Select Number 0 Master 1 Slave Head Address Binary HS2 HS1 HS0 HS3 DRV 1 0 RSVD Reserved LSB MSB...

Страница 25: ...hard reset as opposed to CNTRL ALT DEL or at the activation of the software reset through the digital output register After the host writes to the command register with a read read long read buffer se...

Страница 26: ...ek complete status DRQ Data Request This bit indicates that the drive is ready to transfer a word or byte of data from the host to the data port CORR Corrected Data This bit is set when the drive enco...

Страница 27: ...1h 22h 23h 40h 41h 1Xh 7Xh C6h E8h C5h 30h 31h 32h 33h F0h F0h F0h D Y Y Y D Y Y D Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y D Y Y D Y D Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y...

Страница 28: ...Drive Seek Complete Error Corrected Data Index Drive Write Fault CORR IDX ERR DRQ DSC DWF DRDY BSY Drive Ready Busy Alternate Status Register Digital Output Register 3F6h Write 8 bits This register co...

Страница 29: ...ddress Register RSVD Reserved This bit is reserved for floppy disk drive subsystem usage In the original AT implementation the hard disk and floppy disk systems shared this register location The ZT 89...

Страница 30: ...currently selected A logical 0 indicates the respective drive is selected For example if drive 0 is selected then DS0 will be logical 0 active and DS1 will be logical 1 inactive Artisan Technology Gr...

Страница 31: ...drives are daisy chained one must be jumpered as the master and one as the slave When a single drive is attached to the interface it must be jumpered as the master To issue a command load the pertine...

Страница 32: ...ector read the read terminates at the sector where the error occurs The command block registers contain the cylinder head and sector number of the sector where the error occurs The host then reads the...

Страница 33: ...rs are 16 bits ECC bytes are 8 bit transfers Verify Sectors 4xh This command works the same as the read sectors command except that no data is transferred Up to 256 sectors are read into the sector bu...

Страница 34: ...this command The drive sets BSY immediately upon receipt of the command If the drive is a master it performs the diagnostic tests and saves the results The drive then checks for the presence of a slav...

Страница 35: ...blocks or the block count requested If this sector count is not evenly divisible by the block count as many full blocks as possible are transferred followed by a final partial block transfer The part...

Страница 36: ...locks are not transferred Interrupts are generated when DRQ is set at the beginning of each block or partial block Set Multiple Code C6h This command enables the controller to perform read and write m...

Страница 37: ...to the buffer Identify Drive ECh The identify command allows the host to receive parameter information from the drive When the command is issued the drive sets BSY stores the required parameter inform...

Страница 38: ...d bytes sector Word 06 Number of physical sectors track Word 07 Vendor unique Word 08 Vendor unique Word 09 Vendor unique Word 10 19 Serial number Word 20 Buffer type Word 21 Buffer size in 512 byte i...

Страница 39: ...ther to generate the signals that initialize the hardware Once the reset has been removed and the drive has been re enabled with BSY still active the drive will perform any necessary hardware initiali...

Страница 40: ...set or reset the BSY flip flop When BSY is inactive the host has read and write access to all command block registers Data Retry Algorithm When an ECC error is detected in the data field during a read...

Страница 41: ...f time for 20 retries is 0 34 seconds 17 ms 20 340 ms Header retries cannot be disabled from the interface nor can the header retry count be changed ERROR REPORTING In general errors are detected in t...

Страница 42: ...Seek V V V V V V Execute Drive Diagnostics V V Initiator Drive Parameters V Read Multiple V V V V V V V V V Write Multiple V V V V V V V Set Multiple V V Read Buffer V V Write Buffer V V Identify Dri...

Страница 43: ...ing only two jumper posts are labeled Wx where x defines the jumper number Jumpers having three jumper posts are labeled Wx a and b These jumpers have two possible selections where a is one selection...

Страница 44: ...following figure Customer Jumper Locations is used to document customer specific configurations W2 W9 ZT 8952 REV 0 2 W10 W11 W12 W13 W14 W1 W3 W4 W5 W6 W7 W8 J2 J1 J4 J3 A B LED Note W2 in for 16 bit...

Страница 45: ...ons 44 W2 W9 ZT 8952 REV 0 2 W10 W11 W12 W13 W14 W1 W3 W4 W5 W6 W7 W8 J2 J1 J4 J3 A B LED W15 ZIATECH Customer Jumper Locations Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC...

Страница 46: ...ntroller Logic W9 Frontplane Interrupt Selection W3 W7 IDE Diagnostic W8 IDE Interrupt Mode W10A W10B IRQx Polarity Selection W1 JUMPER DESCRIPTIONS W1 Selects the polarity of the Slot Specific Interr...

Страница 47: ...t 16 Bit Transfer Jumper Factory default is installed Install W2 in systems with ZT 8911 ZT 8902 ZT 8901 and STD 32 CPUs performing 16 bit transfers W2 FUNCTION IN BHE enabled OUT BHE ignored Controll...

Страница 48: ...JUMPER IN FUNCTION W3 FP7 enabled W4 FP6 enabled W5 FP5 enabled W6 FP3 enabled W7 FP1 enabled Interrupt Logic W7 W6 W5 W4 W3 2 FP1 4 FP3 6 FP5 8 FP6 10 FP7 J 3 W11 W12 W13 W14 E47 P37 P44 P50 INTRQ1 I...

Страница 49: ...s W10A enables and drives the interrupt active W10B drives the interrupt active but does not enable gate it on the backplane unless the SLV ACT signal is driven high by the IDE interface This maintain...

Страница 50: ...ol logic Removing this jumper lets a drive be powered by the ZT 8952 but controlled via an external IDE interface Removing the jumper does not let the board drive the backplane with data during backpl...

Страница 51: ...iate Contact Ziatech for further details on individual drives The term typical when used with current requirements for integrated drives means the sum of base controller typical ZT 8952 0 plus the Ran...

Страница 52: ...o 55 8 to 80 8 to 80 10 000 10 000 40 000 40 000 150 150 A V G S E E K m s 19 17 19 17 Obsolete Data provided for reference ZT 8952 40 1580 10 000 40 000 880 40 to 60 5 to 55 8 to 80 100 0 7 75 2 5 0...

Страница 53: ...E INPUT LOAD MNEMONIC PIN COMPONENT SIDE OUTPUT DRIVE INPUT LOAD MNEMONIC E9 E11 E13 E15 E50 E52 E54 E56 DMAIOR EX8 START EX32 E58 E60 E62 E64 E57 E59 E61 E63 DMAIOW IO16 CMD EX16 E66 E68 E70 E72 E65...

Страница 54: ...NPUT LOAD MNEMONIC PIN COMPONENT SIDE OUTPUT DRIVE INPUT LOAD MNEMONIC E9 E11 E13 E15 E50 E52 E54 E56 DMAIOR EX8 START EX32 E58 E60 E62 E64 E57 E59 E61 E63 DMAIOW IO16 CMD EX16 E66 E68 E70 E72 E65 E67...

Страница 55: ...0 010 Board Width 4 500 0 010 Board Thickness 0 062 0 008 Board dimensions are shown in figure Board Dimensions below COMPONENT SIDE 6 50 25 4 50 2 X 0 400 3 610 0 06 R MAX 2 PL 0 15 X 45 CHAM 3 PL 0...

Страница 56: ...0 0625 inches Component Side Solder Side STD 32 STD 32 E01 E03 E05 E07 E09 E11 E02 E04 E06 E08 E10 E12 E71 E73 E75 E77 E79 E72 E74 E76 E78 E80 E13 E14 P01 P02 E15 E16 P03 P04 E17 E18 P05 P06 E19 E20 P...

Страница 57: ...aining are in common with those of J1 and comprise the control interface for the IDE interface The table J1 and J2 Pin Assignments shows the signal definition for both J1 and J2 J3 Frontplane Interrup...

Страница 58: ...SLV ACT VCC GND 42 44 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND Host Data 8 Host Data 9 Host Data 10 Host Data 11 Host Data 12 Host Data 13 Host Data 14 Host Data 15 Key GND GND...

Страница 59: ...B Specifications 58 ZIATECH Assembly Diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 60: ...Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y D Y Y D Y D Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Key SC Sector Count Register SN Sector Number Register Y indicates that the register contai...

Страница 61: ...d for chaining interrupts from one card to another IDE Integrated Drive Electronics IDE refers to a disk drive that has the control logic embedded on the drive itself There are many types of IDE drive...

Страница 62: ...pe STD bus The collection of signals defined on P connector to support 8 bit transfers between masters and slaves STD 32 bus The extension to the STD bus to support 8 bit 16 bit and 32 bit transfers b...

Страница 63: ...takes extra care in the design of the product in order to ensure reliability The product was designed in top down fashion using the latest in hardware and software design techniques so that unwanted...

Страница 64: ...immediately void the warranty for that particular product 4 Mark the RMA number clearly on the outside of the box ZIATECH WARRANTY Warranty information for Ziatech products is available at Ziatech s...

Страница 65: ...e San Luis Obispo CA 93401 USA Tel 805 541 0488 FAX 805 541 5088 E Mail tech_support ziatech com Internet http www ziatech com Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE...

Страница 66: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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