Ziatech Corporation ZT 8808A, Руководство по эксплуатации

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Theory of Operation
RESET
The ZT 8809A is equipped with a System Reset circuit that asserts the
STD bus SYSRESET* signal at any time DC voltage is less than
4.75 V. It also drives the SYSRESET* signal during the time a
pushbutton switch drives the PBRESET* STD bus signal to the
ZT 8809A.
The pushbutton switch is first debounced on the
ZT 8809A before causing a system reset. The pushbutton must
remain depressed a minimum of 0.5 microseconds for the debounce
circuit to detect it properly. This limitation remains true for an open-
collector logic gate driving PBRESET*, with the additional restriction
that the gate must be able to sink 0.2 mA.
During a reset, the CPU, the two serial ports, and the printer port are
reset to initial states (these states are detailed in the descriptions of
each of these devices later in this manual). No other devices are
affected by the system reset. The SYSRESET* signal is driven to a
logical low for a minimum of 200 milliseconds (and typically
500 milliseconds) on power-up after the power supply reaches 4.75 V.
On power-up, also, the STD bus DCPWRDWN* signal (pin 5) is
monotonically driven to a logical 0 until power is at 4.75 V. If power
falls below 4.75 V, DCPWRDWN* is again driven to a logical 0.
This signal may be used by external boards protecting their RAM
during power-fail.
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