CLM920_RC3(RV3 RE3)LCC Series CAT1 Module Hardware Manual
Shanghai YUGE Information Technology Co., Ltd.
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pulling down PWRKEY for at least 100ms. Users can determine whether the module is
powered on by querying the high and low levels of the VDD_EXT pin.
Table 3-6 Pin definition of switch
Pin
Signal name
I/O
High level value
Description
21
PWRKEY
DI
VBAT-0.3V
Active low
3.4.2 Boot sequence
Figure 3-7 Power-on sequence diagram
Table 3-7 Power-on sequence parameters
Symbol
Description
Min
Typical
Max
unit
Ton
Low level width when Booting
100
500
ms
Ton(status)
Boot time (judging by status)
TBD
s
Ton(usb)
Boot time (judging by usb status)
12
s
VIH
PWRKEY input high level
0.6
0.8
1.8
V
VIL
PWRKEY input low
-0.3
0
0.5
V
推荐使用开集驱动电路来控制
PWRKEY
,在拉高基极电平至少
100ms
后可以释放,
此时模块开机。也可以通过按钮进行开机设计,此时按钮附近需要放置一个
TVS
管用
于
ESD
保护。