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The selected memory byte cannot be used for temporary data storage.
n
Number of Memory bytes from MB0: Enter the number of retentive memory bytes
from memory byte 0 onwards.
n
Number of S7 Timers from T0: Enter the number of retentive S7 timers from T0
onwards. Each S7 timer occupies 2bytes.
n
Number of S7 Counters from C0: Enter the number of retentive S7 counter from C0
onwards.
n
Areas: This parameter is not supported.
n
Priority: Here the priorities are displayed, according to which the hardware interrupt
OBs are processed (hardware interrupt, time-delay interrupt, async. error interrupts).
n
Priority: The priority may not be modified.
n
Active: Activate the check box of the time-of-day interrupt OBs if these are to be auto-
matically started on complete restart.
n
Execution: Select how often the interrupts are to be triggered. Intervals ranging from
every minute to yearly are available. The intervals apply to the settings made for
start
date
and
time
.
n
Start date/time: Enter date and time of the first execution of the time-of-day interrupt.
n
Process image partition: This parameter is not supported.
n
Priority: Here the priorities may be specified according to which the corresponding
cyclic interrupt is processed. With priority "0" the corresponding interrupt is deacti-
vated.
n
Execution: Enter the time intervals in ms, in which the watchdog interrupt OBs should
be processed. The start time for the clock is when the operating mode switch is
moved from STOP to RUN.
n
Phase offset: Enter the delay time in ms for current execution for the watch dog inter-
rupt. This should be performed if several watchdog interrupts are enabled. Phase
offset allows to distribute processing time for watchdog interrupts across the cycle.
n
Process image partition: This parameter is not supported.
n
Level of protection: Here 1 of 3 protection levels may be set to protect the CPU from
unauthorized access.
–
Protection level 1 (default setting):
No password adjustable, no restrictions
–
Protection level 2 with password:
Authorized users: read and write access
Unauthorized user: read access only
–
Protection level 3:
Authorized users: read and write access
Unauthorized user: no read and write access
5.9 Project transfer
There are the following possibilities for project transfer into the CPU:
Retentive Memory
Interrupts
Time-of-day interrupts
Cyclic interrupts
Protection
Overview
VIPA System 300S
+
Deployment CPU 312-5BE23
Project transfer
HB140 | CPU-SC | 312-5BE23 | en | 18-45
52