Yamaha YSP-1100U, Руководство по обслуживанию

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A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
YSP-1100
62
★
All voltages are measured with a 10M
Ω
/V DC electronic volt meter.
★
Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
DSP 2/3
3.3
3.0
3.3
3.0
3.0
0
3.0
3.0
3.3
3.0
3.0
0
3.1
3.3
3.3
3.3
3.3
3.3
0
0
0
0
3.2
3.2
3.2
3.3
0
0
0
0
0
0
0
0
0
3.3
3.1
0
0
1.6
1.2
3.1
3.1
3.2
3.2
3.2
0
3.3
0
3.0
3.1
3.1
3.0
2.9
3.0
2.9
3.0
3.3
2.9
3.1
3.2
3.0
3.0
3.0
3.1
3.0
3.3
0
3.3
0
0
3.0
0
2.9
3.3
2.9
2.9
0
3.2
3.0
3.3
3.1
0
3.1
1.7
0
0
0
1.6
1.2
3.1
3.1
0
3.3
1.3
0
3.3
3.3
3.3
3.3
0
1.3
0
1.3
0
1.7
1.7
1.7
0.8
1.6
1.7
1.3
0
1.3
0
1.6
1.3
0
0
1.3
3.3
0
1.3
3.3
3.3
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
0
3.2
0.1
1.3
0
0.7
1.3
1.3
0
3.3
1.7
1.7
3.3
0.5
0
1.3
3.0
3.0
3.0
3.0
3.0
3.0
3.3
0
1.3
3.1
3.1
3.0
3.2
3.0
2.9
2.9
1.3
0
3.3
3.1
3.0
2.9
3.1
0
3.1
3.3
0
1.3
1.3
0
3.3 3.3 3.3 3.3
0
1.3
0
3.2 3.2 3.3
0
1.3 3.3
0
3.3
1.7
0
3.3
1.3
0
3.3
3.3
0 0
3.3
0
1.3
0 0 0 0 0 0
1.3
0
3.3
0 0 0
3.3 1.3
1.3 0 3.3
1.6
0 1.3 1.3 0 0.1 0.1 0.1 1.3 0 3.3 0.1 3.3 3.3 0 3.3
0
1.3
3.2
0
3.3
1.3 0 1.3
3.3
3.3 0
3.3
0
0 1.3
0
0
3.1
3.3
0
3.3 3.3
0
0.1 0.1
3.3
0.1
0
0.1
DSP
DSP2
DRAM
FLASH
No replacement part available.
サービス部品供給なし
Pin Multiple
xing
EMIF32
L1P Cache
Direct Mapped
4K Bytes Total
Digital Signal Processors
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
Power-Down
Logic
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path B Data Path A
B Register File
Control
Registers
C67x TM CPU
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Test
A Register File
.L1t
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
.S1t .M1t .D1 .D2 .M2t .S2t .L2t
GP1
GP0
HPI16
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
Total
IC12 : D60YA003BPYP225
Decoder
IC13 : SN74AHC1G08DCKR
2-input AND gate
IC16 : W9864G6EH-7
1M x 4 banks x 16 bits SDRAM
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
ROWDECODER
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
ROWDECODER
COLUMN DECODER
SENSE AMPLIFIER
COLUMN DECODER
SENSE AMPLIFIER
ROWDECODER ROWDECODER
IC17 : S29AL016D70TFI0
16M-bit COMS 3.0 volt-only boot sector flash memory
Y 4
B 2
GND 3
Vcc 5 A 1
In put/ Out put
Buff ers
X- Decoder
Y-Decoder
Chip Enab le
Out put Enable
Logi c
Erase V olt ag e
Generat or
PGM Vo ltag e
Generator
Tim er
V
CC
De te ct or
State
Contr ol
Comm and
Regi st er
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0–DQ15 (A-1)
Sect or Sw itc hes
RY/ BY#
RESET#
Data
Lat ch
Y- Gating
Cell M atrix
Addr
e
ss
La
tc
h
A0– A19