Yamaha TF1, Руководство по обслуживанию

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TF5/TF3/TF1
143
7-3-3. CPLD_MUTE
[Contents]
Inspect the connection of MUTEOUT[1][2] port of CPLD
and DSP#1-#5 and PIC.
[Procedure]
<GUI>
Automatic judgment
<Display of inspection log>
In the case of PASS, “PASS: CPLD_MUTE”.
In the case of FAIL, the contents of failure are returned like
“FAIL: IC101(T10) IC101(B10)”.
Display and response to contents corresponding to the
FAIL are as follows.
IC101(T10) MUTEOUT[1](68
th ) of CPLD(IC802) and
GP1[4](T10) of DSP#1(IC101)
IC101(B10) MUTEOUT[2](69 th ) of CPLD(IC802) and
GP1[5](B10) of DSP#1(IC101)
IC201(T10) MUTEOUT[1](68
th
) of CPLD(IC802) and
GP1[4](T10) of DSP#2(IC201)
IC201(B10) MUTEOUT[2](69 th ) of CPLD(IC802) and
GP1[5](B10) of DSP#2(IC201)
IC301(T10) MUTEOUT[1](68
th
) of CPLD(IC802) and
GP1[4](T10) of DSP#3(IC301)
IC301(B10) MUTEOUT[2](69 th ) of CPLD(IC802) and
GP1[5](B10) of DSP#3(IC301)
IC401(T10) MUTEOUT[1](68 th ) of CPLD(IC802) and
GP1[4](T10) of DSP#4(IC401)
IC401(B10) MUTEOUT[2](69 th ) of CPLD(IC802) and
GP1[5](B10) of DSP#4(IC401)
IC501(T10) MUTEOUT[1](68 th ) of CPLD(IC802) and
GP1[4](T10) of DSP#5(IC501)
IC501(B10) MUTEOUT[2](69
th
) of CPLD(IC802) and
GP1[5](B10) of DSP#5(IC501)
IC651(18) MUTEOUT[2](69 th ) of CPLD(IC802) and
RB7(18 th ) of PIC(IC651)
7-3-4. PLL
[Contents]
It is determined by checking that PLL is locked correctly
when internal clock is selected as the master clock, and that
PLL is unlocked when external clock without an input is
selected as the master clock, and the locked/unlocked state
is determined by checking with GPIO1 [22] (U15) of CPU
(IC905).
[Procedure]
<GUI>
Automatic judgment
<Display of inspection log>
In the case of PASS, “PASS: PLL”.
In the case of FAIL, “FAIL: PLL”.
7-4. SLOT
The example of a screen of MAINCOM circuit board test.
It inspects using SLOT jigs for the inspection.
Contents of the test are currently undecided.