A
B
C
D
E
F
G
H
1
2
3
4
5
6
STAGEPAS 500
9
■
STAGEPAS 500 CIRCUIT DIAGRAM 6/9 (DSP 1/2)
■
STAGEPAS 500 CIRCUIT DIAGRAM 6/9 (DSP 1/2)
N.M: not installed
(未実装)
DSP
1/2
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G-2
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to CONTROL2 (2/3)-CN27 (Page 7: G-2 )
not installed
not installed
OP AMP
SYSTEM RESET
ADC
DAC
CPU
(SWL01B)
MASK ROM
8M
OP AMP
1/2
2/2
OP AMP
OP AMP
1/2
2/2
REG3.3V
REG2.5V
ZA1G3A00604
4
RH5RZ25CA-T1 (X8571A00)
REG2.5V
DSP: IC1005
1
2
3
1. GND
2. INPUT
3. OUTPUT
µ
PC2933AT (X8572A00)
REG3.3V
DSP: IC1006
1: V in
2: GND
3: V out
1
2
3
DTA114EKA (WJ613800)
DIGITAL TRANSISTOR
DSP: Q1002
1
3
2
1: GND(+)
2: IN
3: OUT
R
1
R
2
IN
GND(+)
OUT
IN
GND(+)
OUT
DTC114EKA (WJ614000)
DIGITAL TRANSISTOR
DSP: Q1001
1: GND
2: IN
3: OUT
2
3
1
R
1
R
2
IN
GND
OUT
IN
GND
OUT
2SC3326 (WJ612800)
TRANSISTOR
DSP: Q1003, 1004
1
3
2
1: BASE
2: EMITTER
3: COLLECTOR
1
2
3