16
STAGEPAS 500
LSI PIN DESCRIPTION
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Vss
TESTN
PLLBPN
PLLV
DD
CIN
PLLVss
TRSTN
TMS
TCK
TDI
TDO
XI
XO
Vss
V
DD
ICN
ECSN
EWRN/PD5
ERDN/PD4
EA3/PD3
EA2/PD2
EA1/PD1
EA0/PD0
IOV
DD
ED0/PC0
ED1/PC1
ED2/PC2
ED3/PC3
ED4/PC4
ED5/PC5
ED6/PC6
ED7/PC7
Vss
IRQ0N/PH0
TxD0
RxD0
TxD1/PG2
RxD1/PH1
SCLK1/PH2
SDO
SDI/PH3
BCLK
WCLK/SYO
SYSCLK/PG3
Vss
V
DD
IOV
DD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Vss
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7/SYI
-
I
I
-
-
-
I
I
I
I
O
I
O
-
-
I
I
I
I
I
I
I
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I
O
I
O
I
I
O
I
O
O
O
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
Input for TEST
PLL bypass select
PLL Power 2.5 V
Capacitor terminal for PLL
PLL Ground
JTAG input
JTAG output
Crystal oscillator
Crystal oscillator
Ground
Power 2.5 V
Hardware reset
CPU I/F chip select
CPU I/F write enable / Port D
CPU I/F read enable / Port D
CPU I/F address bus / Port D
Power 3.3 V
CPU I/F data bus / Port C
Ground
Interrupt input / Port H
Serial output
Serial input
Serial output / Port G
Serial input / Port H
External synchronization clock / Port H
Serial output
Serial input / Port H
Bit clock output
Word clock output
Clock output / Port G
Ground
Power 2.5 V
Power 3.3 V
I/O port A
Ground
I/O port B
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Vss
IOV
DD
LBN/LWRN/PF6
UBN/UWRN/PF7
RDN/PF4
MD00
MD08
MD01
MD09
MD02
MD10
MD03
Vss
MD11
MD04
MD12
MD05
MD13
MD06
MD14
MD07
MD15
WRN/PF5
Vss
V
DD
IOV
DD
MA17
MA16
MA15
MA14
MA13
MA12
MA11
MA10
MA09
MA08
MA07
MA06
MA05
Vss
MA04
MA03
MA02
MA01
CS0N/PG0
MA18
MA19
MA21/PF1
MA22/PF2
MA20
MA23/PF3
CSIN/PG1
MA00/PF0
Vss
V
DD
IOV
DD
CS2N/PE0
CS3N/PE1
CS4N/CASN/PE2
CS5N/PE3
CS50RDN/PE4
CS51WRN/PE5
CS52WRN/PE6
CS53WRN/RASN/PE7
-
-
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
-
-
-
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
O
O
O
O
O
O
O
O
Ground
Power 3.3 V
External memory lower-byte enable / Port F
External memory upper-byte enable / Port F
External memory read enable / Port F
External memory data bus
Ground
External memory data bus
Ground
Power 2.5 V
Power 3.3 V
External memory address bus
Ground
External memory address bus
External memory chip select / Port G
External memory address bus
External memory address bus / Port F
External memory address bus
External memory address bus / Port F
External memory chip select / Port G
External memory address bus / Port F
Ground
Power 2.5 V
Power 3.3 V
External memory chip select / Port E
YMW767-VTZ (X6055A00) CPU (SWL01B)
DSP: IC1007
（
LSI
端子機能表
）
