SLG-100N
10
LSI PIN DESCRIPTION
1
MD4
I/O
33
AVDD
-
DC A+5Vs bus
2
MD3
I/O
34
VDD
-
DC D+5V
3
MD0
I/O
External RAM interface data
35
TST0
-
DC D+5V
4
MD1
I/O
36
TST1
-
DC D+5V
5
MD2
I/O
37
DOEN
-
DC D+5V
6
MCKO
O
Master clock output
38
SDO1
O
N.C.
7
XO
O
Crystal oscillator connection
39
SDO0
O
N.C.
8
XI
I
Crystal oscillator connection
40
WC
O
N.C.
9
ER0
I
41
BCO
O
N.C
10
ER1
I
Eary refrection preset select
42
MA0
O
11
ER2
I
43
MA1
O
12
REV0
I
44
MA2
O
13
REV1
I
Effect select
45
MA3
O
14
REV2
I
46
MA4
O
15
MUTEN
I
DC D+5V
47
MA5
O
External RAM interface address
16
ICN
I
Initial clear
48
MA6
O
17
PRG
I
DC D+5V
49
MA7
O
18
MODE
I
Preset mode (H=DC +5V)
50
MA12
O
19
VSS
-
Ground
51
MA14
O
20
AVSS
-
Ground
52
VSS
-
Ground
21
CVA
-
N.C.
53
MA10
O
22
AORL
O
N.C.
54
MA011
O
23
AORR
O
N.C.
55
MA09
O
External RAM interface address
24
CHL
I
Sample hold capacitor connection
56
MA8
O
25
AIL
I
Lch ADC input
57
MA13
O
26
VDD
-
DC D+5V
58
VDD
-
DC D+5V
27
AIR
I
Rch ADC input
59
WEN
I
Write enable
28
CHR
I
Sample hold capacitor connection
60
OEN
I
Output enable
29
AOFL
O
Lch DAC output
61
CEN
I
Chip select
30
AOFR
O
Rch DAC output
62
MD7
I/O
31
AVDD
-
DC A+5V
63
MD6
I/O
External RAM interface data
32
CVB
I
Rch midpoint voltage
64
MD5
I/O
PIN
NAME
I/O
FUNCTION
NO.
PIN
NAME
I/O
FUNCTION
NO.
YSS234
MA: IC01
DSP
(XN299A00)
(Digital Sound Processor)
IC BLOCK DIAGRAM
NJM3404AM (XM527A00)
Dual Operational Amplifier
MA: IC08-13
PUP: IC15
NJM3414AM (XR294A00)
Dual Operational Amplifier
MA: IC14
1
2
3
4
-V
8
7
6
5
Output A
+V
Non-Inverting
Input A
-DC Voltage Supply
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
1
2
3
4
-V
8
7
6
5
Output A
+V
Non-Inverting
Input A
Ground
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
