Yamaha RX-V675, Руководство по обслуживанию

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Pin No. Function Name I/O Detail of Function
Reset (active low). When asserted, the chip is placed in the reset state and the peripheral pins are
configured as inputs. After deassertion of NRESET, the chip is clocked by XTALI and starts booting from the
port configured by the FCLE, FALE pins.
D13 NRESET I
The NRESET signal must be asserted after power-up.
K3 XTALI I Oscillator circuit input. Internal system clock will be derived from XTALI (internal clock multiplier).
J3 XTALO O Oscillator circuit output.
C7 RREF I Reference current. Connect a 3.0 k-ohms ±1% resistor to GND.
B10 TEST1 I Reserved. Connect to VDD for normal operation.
A10 HIGHZ I Reserved. Connect to VDD for normal operation.
E4
F4
G4
H4
J4
V1
n.c. – Pins must be left unconnected (18x).
A4
A5
B4
B5
C8
C9
Pin No. Function Name I/O Detail of Function
J2
VCO[1:0] I
External oscillator inputs, typically coming from an external VCO. Together with the external loop-filter and
the internal clock dividers, each PDOUT/VCO pair can form a complete PLL.
K2
J1
PDOUT[1:0] O
Phase discriminator outputs. These signals are charge-pump type outputs.
K1 Each of them can be used to feed the loop-filter of a PLL structure.
Pin No. Function Name I/O Detail of Function
D12
C12
B12
A12
SSMD[7:0] I/O Data lines.
D11
C11
B11
A11
C10 SSMCLK O Clock output.
A13 SSMCMD O Command output.
D10 SSMCP I Card power input (high = off).
D9 SSMWP I Write protect input (low = protect).
SSM Interface
External PLL Pins
Global Pins
JTAG Interface
Pin No. Function Name I/O Detail of Function
B15 TMS I JTAG mode select.
C14 TCK I JTAG clock.
A16 TDI I JTAG serial data input.
A15 TDO O JTAG serial data output.
85
RX-V675/HTR-6066/RX-A730/TSR-6750
RX-V675/HTR-6066/
RX-A730/TSR-6750