Yamaha RX-V483/HTR-4071, Руководство по обслуживанию

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RX-V483/HTR-4071
RX-V483/HTR-4071
Digital Video Inputs Pins
Pin
No. Function
Name
I/O Detail of Function
3 D0 I (PD*)
REC 656 Video Data Inputs
4 D1 I (PD*)
5 D2 I (PD*)
6 D3 I (PD*)
7 D 4 I (PD*)
8 D 5 I (PD*)
10 D 6 I (PD*)
11 D7 I (PD*)
13 9 PCL K IN I (PD*) PCL K IN I (PD*) Pixel clock input
*PD: Pull Down Resistance embedded
Audio Inputs / Outputs Pins
Pin
No. Function
Name
I/O Detail of Function
131 C H 0ABCL K I (PD*)
LPCM Audio Bit Clock
/ DSD Clock
132 C H 0ALRCL K I (PD*)
LPCM Audio Word Clock
/ DSD Data (Left 2)
133 C H 0ASD3 I (PD*)
LPCM Audio Data (for RLC, RRC (FLC, FRC) )
/ IEC
6 0 958 Data
/ DSD Data (Right 0)
13 4 C H 0ASD2 I (PD*)
LPCM Audio data (for RL, RR)
/ DSD Data (Left 1)
13 5 C H 0ASD1 I (PD*)
LPCM Audio Data (for FC, LFE)
/ DSD Data (Right 1)
13 6 C H 0ASD0 I (PD*)
LPCM Audio data (for LF, RF)
/ DSD Data (Left 0)
12 9 C H 0AMCL K I (PD*) Audio Master Clock
37 C H 1ABCL K I (PD*)
LPCM Audio Bit Clock
/ DSD Data (Right 2)
3 6 C H 1ALRCL K I (PD*)
LPCM Audio Word Clock
/ DSD Data (Right 3)
3 5 C H 1ASD0 I (PD*)
LPCM Audio data (for LF, RF)
/ IEC
6 0 958 Data
/ DSD Data (Left 3)
*PD: Pull Down Resistance embedded
TMDS Differential Outputs Pins
Pin
No. Function
Name
I/O Detail of Function
32 P0TXCM O TMDS TX port 0 Clock –
30 P0TXCP O TMDS TX port 0 Clock +
2 9 P0TX0M O TMDS TX port 0 C H 0 data –
27 P0TX0P O TMDS TX port 0 C H 0 data +
2 6 P0TX1M O TMDS TX port 0 C H 1 data –
2 4 P0TX1P O TMDS TX port 0 C H 1 data +
23 P0TX2M O TMDS TX port 0 C H 2 data –
21 P0TX2P O TMDS TX port 0 C H 2 data +
Audio Pins
Pin
No. Function
Name
I/O Detail of Function
9 3 P0RXCM I TMDS RX port 0 clock –
94 P0RXCP I TMDS RX port 0 clock +
96 P0RX0M I TMDS RX port 0 C H 0 data –
9 7 P0RX0P I TMDS RX port 0 C H 0 data +
99 P0RX1M I TMDS RX port 0 C H 1 data –
100 P0RX1P I TMDS RX port 0 C H 1 data+
102 P0RX2M I TMDS RX port 0 C H 2 data –
103 P0RX2P I TMDS RX port 0 C H 2 data +
8 0 P1RXCM I TMDS RX port 1 clock –
8 1 P1RXCP I TMDS RX port 1 clock +
8 3 P1RX0M I TMDS RX port 1 C H 0 data –
84 P1RX0P I TMDS RX port 1 C H 0 data +
86 P1RX1M I TMDS RX port 1 C H 1 data –
8 7 P1RX1P I TMDS RX port 1 C H 1 data+
89 P1RX2M I TMDS RX port 1 C H 2 data –
9 0 P1RX2P I TMDS RX port 1 C H 2 data +
55 P2RXCM I TMDS RX port 2 clock –
56 P2RXCP I TMDS RX port 2 clock +
58 P2RX0M I TMDS RX port 2 C H 0 data –
59 P2RX0P I TMDS RX port 2 C H 0 data +
6 1 P2RX1M I TMDS RX port 2 C H 1 data –
6 2 P2RX1P I TMDS RX port 2 C H 1 data+
64 P2RX2M I TMDS RX port 2 C H 2 data –
65 P2RX2P I TMDS RX port 2 C H 2 data +
4 2 P3RXCM I TMDS RX port 3 clock –
4 3 P3RXCP I TMDS RX port 3 clock +
45 P3RX0M I TMDS RX port 3 C H 0 data –
46 P3RX0P I TMDS RX port 3 C H 0 data +
48 P3RX1M I TMDS RX port 3 C H 1 data –
49 P3RX1P I TMDS RX port 3 C H 1 data+
5 1 P3RX2M I TMDS RX port 3 C H 2 data –
5 2 P3RX2P I TMDS RX port 3 C H 2 data +
DDC I/F Pins
Pin
No. Function
Name
I/O Detail of Function
1 44 TX0SCL I/O TX port 0 DDC clock*
1 TX0SDA I/O TX port 0 DDC data*
10 8 RX0SCL I/O RX port 0 DDC clock*
107 RX0SDA I/O RX port 0 DDC data*
10 6 RX1SCL I/O RX port 1 DDC clock*
10 5 RX1SDA I/O RX port 1 DDC data*
77 RX2SCL I/O RX port 2 DDC clock*
7 6 RX2SDA I/O RX port 2 DDC data*
7 5 RX3SCL I/O RX port 3 DDC clock*
7 4 RX3SDA I/O Rx port 3 DDC data*
* Because this is an open drain pin, it should be pulled up externally.