Yamaha rx-sl100, Руководство по обслуживанию

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RX-SL100/RX-SL100RDS
42
No. Name I/O Function
1 AVSS1 I Ground for Analog Logic of PLLDCK (GND)
2 AVDD1 I Power Supply for Analog Logic of PLLDCK (+3.3 V)
3 A23 I CPU Address Bus bit 23 (for CSMEM)
4 A22 I CPU Address Bus bit 22 (for CSMEM)
5 A21 I CPU Address Bus bit 21 (for CSMEM)
6 A20 I CPU Address Bus bit 20 (for CSMEM)
7 A19 I CPU Address Bus bit 19 (for CSMEM)
8 VSS I Ground for Digital Logic & I/O (GND)
9 A18 I CPU Address Bus bit 18 (for CSMEM)
10 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
11 A17 I CPU Address Bus bit 17 (for CSMEM)
12 A16 I CPU Address Bus bit 16 (for CSMEM)
13 A15 I CPU Address Bus bit 15 (for CSMEM)
14 A14 I CPU Address Bus bit 14 (for CSMEM)
15 A13 I CPU Address Bus bit 13 (for CSMEM)
16 A12 I CPU Address Bus bit 12 (for CSMEM)
17 A11 I CPU Address Bus bit 11 (for CSMEM)
18 A10 I CPU Address Bus bit 10 (for CSMEM)
19 A9 I CPU Address Bus bit 9 (for CSMEM)
20 VSS I Ground for Digital Logic & I/O (GND)
21 A8 I CPU Address Bus bit 8 (for CSMEM)
22 A7 I CPU Address Bus bit 7 (for CSMEM and CSREG)
23 A6 I CPU Address Bus bit 6 (for CSMEM and CSREG)
24 A5 I CPU Address Bus bit 5 (for CSMEM and CSREG)
25 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
26 A4 I CPU Address Bus bit 4 (for CSMEM and CSREG)
27 A3 I CPU Address Bus bit 3 (for CSMEM and CSREG)
28 A2 I CPU Address Bus bit 2 (for CSMEM and CSREG)
29 A1/WR3 I Write Strobe for D31-24 (LWD=1) / Address bit 1 (LWD=0)
30 /WR2 I Write Strobe for D23-16 (LWD=1) / not use (LWD=0) (Unconnected)
31 /WR1 I Write Strobe for D15-8
32 VSS I Ground for Digital Logic & I/O (GND)
33 /WR0 I Write Strobe for D7-0
34 /RD I Read Strobe
35 /RESET I Power On Reset
36 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
37 /CSREG I Chip Select for Register Port Access
38 /CSMEM I Chip Select for Memory Port Access
39 LWD I Select CPU Data Bus Width (32 bits/16 bits)
40 /LEND I Endian Select
41 /SYCKS I System Clock Select (Unconnected)
42 /DREQ O Direct Memory Access Request
43 VSS I Ground for Digital Logic & I/O (GND)
44 /READY O Data Access Ready (Unconnected)
45 /WAIT O Data Access Wait
46 /INT O Interrupt
47 D31 I/O CPU Data Bus (Unconnected)
48 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
49 D30 I/O CPU Data Bus (Unconnected)
50 D29 I/O CPU Data Bus (Unconnected)
51 D28 I/O CPU Data Bus (Unconnected)
52 D27 I/O CPU Data Bus (Unconnected)
53 D26 I/O CPU Data Bus (Unconnected)
54 D25 I/O CPU Data Bus (Unconnected)
55 D24 I/O CPU Data Bus (Unconnected)
56 VSS I Ground for Digital Logic & I/O (GND)
57 D23 I/O CPU Data Bus (Unconnected)
58 D22 I/O CPU Data Bus (Unconnected)
59 D21 I/O CPU Data Bus (Unconnected)
60 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
IC317: YGV619 (DIGITAL P.C.B)
Video Display
No. Name I/O Function
61 D20 I/O CPU Data Bus (Unconnected)
62 D19 I/O CPU Data Bus (Unconnected)
63 D18 I/O CPU Data Bus (Unconnected)
64 D17 I/O CPU Data Bus (Unconnected)
65 D16 I/O CPU Data Bus (Unconnected)
66 VSS I Ground for Digital Logic & I/O (GND)
67 D15 I/O CPU Data Bus
68 D14 I/O CPU Data Bus
69 D13 I/O CPU Data Bus
70 D12 I/O CPU Data Bus
71 D11 I/O CPU Data Bus
72 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
73 D10 I/O CPU Data Bus
74 D9 I/O CPU Data Bus
75 D8 I/O CPU Data Bus
76 VSS I Ground for Digital Logic & I/O (GND)
77 D7 I/O CPU Data Bus
78 D6 I/O CPU Data Bus
79 D5 I/O CPU Data Bus
80 D4 I/O CPU Data Bus
81 D3 I/O CPU Data Bus
82 D2 I/O CPU Data Bus
83 D1 I/O CPU Data Bus
84 D0 I/O CPU Data Bus
85 VSS I Ground for Digital Logic & I/O (GND)
86 SYCKOUT O X’TAL Output for System Clock (Unconnected)
87 SYCKIN I X’TAL Input or Clock generator Input for System Clock
88 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
89 /TEST2 I Test Use Only (Connect to Pull Up Resistance)
90 /TEST1 I Test Use Only (Connect to Pull Up Resistance)
91 /TEST0 I Test Use Only (Connect to Pull Up Resistance)
92 SDQ0 I/O SDRAM Data
93 SDQ15 I/O SDRAM Data
94 SDQ1 I/O SDRAM Data
95 VSS I Ground for Digital Logic & I/O (GND)
96 SDQ14 I/O SDRAM Data
97 SDQ2 I/O SDRAM Data
98 SDQ13 I/O SDRAM Data
99 SDQ3 I/O SDRAM Data
100 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
101 SDQ12 I/O SDRAM Data
102 VSS I Ground for Digital Logic & I/O (GND)
103 SDQ4 I/O SDRAM Data
104 SDQ11 I/O SDRAM Data
105 SDQ5 I/O SDRAM Data
106 SDQ10 I/O SDRAM Data
107 SDQ6 I/O SDRAM Data
108 VSS I Ground for Digital Logic & I/O (GND)
109 SDQ9 I/O SDRAM Data
110 SDQ7 I/O SDRAM Data
111 SDQ8 I/O SDRAM Data
112 DQM0 O SDRAM Data Mask
113 VDD I Power Supply for Digital Logic & I/O (+3.3 V)
114 /WE O SDRAM Write Enable
115 VSS I Ground for Digital Logic & I/O (GND)
116 DQM1 O SDRAM Data Mask
117 /CAS O SDRAM Column Address Strobe
118 SDCLK I/O SDRAM Clock
119 AVSS2 I Ground for Analog Logic of PLLVCK (GND)
120 AVDD2 I Power Supply for Analog Logic of PLLVCK (+3.3 V)
IC317: YGV619 (DIGITAL P.C.B)
Video Display
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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