Yamaha RSio64-D, Руководство по обслуживанию, Страница: 24 / 136

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RSio64-D
XC6SLX100-3FGG676C (YF445A00) FPGA (Field Programmable Gate Array)
DM: IC301
PIN
NO. OUTER
NO.
NAME I/O FUNCTION NAME(DM-IC301) I/O
1 A1 GND - Ground. GND -
2 A2 IO_L1N_VREF_0 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. NC -
3 A3 IO_L1P_HSWAPEN_0 I When Low, enables I/O pullups HSWAPEN /DG -
4 A4 IO_L2N_0 I/O User I/O pin MSWCLK_1 O
5 A5 IO_L4N_0 I/O User I/O pin MY1_SDO3 O
6 A6 IO_L6N_0 I/O User I/O pin MY1_SDI3 I
7 A7 IO_L12N_0 I/O User I/O pin FS256M_1 O
8 A8 IO_L16N_0 I/O User I/O pin MSWCLK_3 O
9 A9 IO_L17N_0 I/O User I/O pin MY3_SDO3 O
10 A10 IO_L22N_0 I/O User I/O pin MY3_SDI1 I
11 A11 IO_L24N_0 I/O User I/O pin SYNCM_3 O
12 A12 IO_L26N_0 I/O User I/O pin FS256M_3 O
13 A13 IO_L34N_GCLK18_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -
14 A14 IO_L35N_GCLK16_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -
15 A15 IO_L37N_GCLK12_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -
16 A16 IO_L38N_VREF_0 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. MSWCLK_2 O
17 A17 IO_L50N_0 I/O User I/O pin MY2_SDI0 I
18 A18 IO_L62N_VREF_0 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. MY2_SDI3 I
19 A19 IO_L63N_SCP6_0 I/O Suspend control pin FS256M_2 O
20 A20 IO_L64N_SCP4_0 I/O Suspend control pin MY4_SDO0 O
21 A21 IO_L65N_SCP2_0 I/O Suspend control pin MY4_SDI1 I
22 A22 IO_L66N_SCP0_0 I/O Suspend control pin FSM_4 O
23 A23 IO_L1N_A24_VREF_5 - • Address A0–A25 BPI address output. These pins become user I/O after configuration.
• These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.
FS128M_4 O
24 A24 TDO O JTAG test date output TDO_FP O
25 A25 IO_L10N_M5A1_5 I/O Memory controller address A[0:14] in bank 5. /RES_FPGA I
26 A26 GND - Ground. GND -
27 B1 IO_L81N_M4A11_4 I/O Memory controller address A[0:14] in bank 4. DNTO[6] O
28 B2 IO_L81P_M4RESET_4 I/O Memory controller reset in bank 4. DNTO[7] O
29 B3 VCCO 0 - Power-supply pins for the output drivers (per bank). VCCO -
30 B4 IO_L2P_0 I/O User I/O pin MY1_SDO0 O
31 B5 GND - Ground. GND -
32 B6 IO_L6P_0 I/O User I/O pin FSM_1 O
33 B7 VCCO 0 - Power-supply pins for the output drivers (per bank). VCCO -
34 B8 IO_L16P_0 I/O User I/O pin MY3_SDO0 O
35 B9 GND - Ground. GND -
36 B10 IO_L22P_0 I/O User I/O pin MY3_SDI2 I
37 B11 VCCO 0 - Power-supply pins for the output drivers (per bank). VCCO -
38 B12 IO_L26P_0 I/O User I/O pin MS256_3 O
39 B13 GND - Ground. NC -
40 B14 IO_L35P_GCLK17_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. - -
41 B15 VCCO 0 - Power-supply pins for the output drivers (per bank). VCCO -
42 B16 IO_L38P_0 I/O User I/O pin MY2_SDO0 O
43 B17 GND - Ground. GND -
44 B18 IO_L62P_0 I/O User I/O pin FSM_2 O
45 B19 VCCO 0 - Power-supply pins for the output drivers (per bank). VCCO -
46 B20 IO_L64P_SCP5_0 I/O Suspend control pin MY4_SDO1 O
47 B21 GND - Ground. GND -
48 B22 IO_L66P_SCP1_0 I/O Suspend control pin SYNCM_4 O
49 B23 IO_L1P_5 I/O User I/O pin FS256M_4 O
50 B24 IO_L10P_M5A0_5 I/O Memory controller address A[0:14] in bank 5. no_use -
51 B25 IO_L12P_M5A3_5 I/O Memory controller address A[0:14] in bank 5. NC -
52 B26 IO_L12N_M5ODT_5 I/O Memory controller on-die termination control for external memory in bank 5. /IRQ_FPGA O
53 C1 IO_L79N_M4A9_4 I/O Memory controller address A[0:14] in bank 4. DNTO[4] O
54 C2 IO_L79P_M4A8_4 I/O Memory controller address A[0:14] in bank 4. DNTO[5] O
55 C3 IO_L83N_VREF_4 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. DEBLED[0] I
56 C4 IO_L83P_4 I/O User I/O pin MY1_SDO1 O
57 C5 IO_L4P_0 I/O User I/O pin MY1_SDI0 I
58 C6 IO_L8N_VREF_0 - These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed
(per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. SYNCM_1 O
59 C7 IO_L12P_0 I/O User I/O pin MS256_1 O
60 C8 IO_L14N_0 I/O User I/O pin MY3_SDO1 O
61 C9 IO_L17P_0 I/O User I/O pin MY3_SDI0 I
62 C10 IO_L19N_0 I/O User I/O pin MY3_SDI3 I
63 C11 IO_L24P_0 I/O User I/O pin FS64M_3 O
64 C12 IO_L31N_0 I/O User I/O pin MSSYNC_3 O
65 C13 IO_L34P_GCLK19_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -
66 C14 IO_L36N_GCLK14_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -
67 C15 IO_L37P_GCLK13_0 I These clock pins connect to global clock buffers.
These pins become regular user I/Os when not needed for clocks. NC -