Yamaha PSR-S750, Руководство по обслуживанию

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37
PSR-S750/PSR-S950
PIN
NO.
I/O FUNCTION NAME
ISL85033IRTZ-T (YD766A00) DC-DC CONVERTER
DM: IC902 (PSR-S950)
O
I
O
-
I
O
I
I
O
O
I
-
-
I
O
-
COMP1, COMP2
FB1, FB2
SS1, SS2
PGND1, PGND2
BOOT1, BOOT2
PHASE1, PHASE2
VIN1, VIN2
EN1, EN2
VCC
SYNCOUT
SYNCIN
SGND
NC
FS
PGOOD1, PGOOD2
PD
COMP1/COMP2 is the output of the error amplifier.
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier.
COMP is the output of the error amplifier. The output voltage is set by an external resistor divider
connected to FB.
In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1/2 to
monitor the regulator output voltage.
Soft-Start pins for each controller. The SS1/2 pins control the soft-start and sequence of their
respective outputs. A single capacitor from the SS pin to ground determines the output ramp rate.
See the “Application Guidelines” on page 18 for soft-start and output tracking/sequencing details.
If SS pins are tied to VCC, an internal soft-start of 2ms will be used.
Power ground connections. Connect directly to the system GND plane.
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor
provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an external
capacitor from this pin to PHASE.
Switch node output. It connects the source of the internal power MOSFET with the external
output inductor and with the cathode of the external diode.
The input supply for the power stage of the PWM regulator and the source for the internal linear
regulator that provides bias for the IC. Place a minimum of 10μF ceramic capacitance from each
VIN to GND and close to the IC for decoupling.
PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to
ground. When the voltage on this pin rises above 2V, the PWM controller is enabled.
Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7μF ceramic
capacitor.
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger).
SYNCIN is not allowed to be floating.
When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase.
When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase.
When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase.
Signal ground connections. The exposed pad must be connected to SGND and soldered to the
PCB. All voltage levels are measured with respect to this pin.
This is a no connection pin.
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND
for adjustable frequency from 300kHz to 2MHz.
Open drain power good output that is pulled to ground when the output voltage is below
regulation limits or during the soft-start interval. There is an internal 5M
Ω
internal pull-up resistor.
The exposed pad must be connected to the system GND plane with as many vias as possible for
proper electrical and thermal performance.
1, 21
2, 20
3, 19
4, 18
5, 17
6, 7,15,16
8, 9, 13, 14
10, 12
11
23
24
25
26
27
22, 28
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