DVR-S60/NX-SW60
62
DVR-S60
NX-SW60
IC500 M37903S4CHP (16-bit C-Mos Micro Computer)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P8
1
/CTS
0
/CLK
0
P8
0
/CTS
0
/RTS
0
/INT
3
P8
7
/T
X
D
1
P8
6
/R
X
D
1
P8
5
/CTS
1
/CLK
1
P1
5
/D
5
/LA
5
P1
4
/D
4
/LA
4
P1
3
/D
3
/LA
3
P1
6
/D
6
/LA
6
P1
7
/D
7
/LA
7
P2
0
/D
8
P10
3
/A
3
P10
2
/A
2
P10
1
/A
1
P10
0
/A
0
P10
5
/A
5
P10
4
/A
4
P10
6
/A
6
P10
7
/A
7
P1
1
0
/A
8
P1
1
1
/A
9
P1
1
2
/A
10
P1
1
3
/A
11
P1
1
4
/A
12
P1
1
5
/A
13
P1
1
6
/A
14
P1
1
7
/A
15
P0
0
/A
16
P0
2
/A
18
P0
4
/A
20
P0
6
/A
22
P0
1
/A
17
P0
3
/A
19
P1
2
/D
2
/LA
2
P1
1
/D
1
/LA
1
P1
0
/D
0
/LA
0
P0
5
/A
21
P0
7
/A
23
V
SS
MD1
P2
1
/D
9
P2
2
/D
10
P2
3
/D
11
P2
4
/D
12
P2
5
/D
13
P2
6
/D
14
P2
7
/D
15
P3
0
/RDY
V
CC
X
OUT
X
IN
V
SS
MD0
RESET
V
CC
V
SS
NMI
AV
CC
AV
SS
V
REF
P8
3
/TxD
0
P8
2
/RxD
0
1
3
2
4
6
5
7
9
8
10
12
11
13
15
14
16
18
17
19
21
20
22
24
23
25
74
72
73
75
71
69
70
68
66
67
65
63
64
62
60
61
59
57
58
56
54
55
53
51
52
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P5
7
/T
A3
IN
/R
TP1
3
/KI
3
P5
3
/T
A1
IN
/R
TP0
3
P5
2
/T
A1
OUT
/R
TP0
2
P5
1
/T
A0
IN
/R
TP0
1
P5
0
/T
A0
OUT
/R
TP0
0
P6
4
/INT
2
P6
3
/INT
1
P6
2
/INT
0
P6
1
/T
A4
IN
P6
0
/T
A4
OUT
P5
6
/T
A3
OUT
/R
TP1
2
/KI
2
P5
5
/T
A2
IN
/R
TP1
1
/KI
4
P5
4
/T
A2
OUT
/R
TP1
0
/KI
0
P7
6
/AN
6
/DA
0
BYTE
CDSEL
P7
5
/AN
5
/(INT
4
)
P7
4
/AN
4
/(INT
3
)
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P7
0
/AN
0
P8
7
/TB2
IN
P8
6
/TB1
IN
P8
5
/TB0
IN
P8
4
/CTS
1
/RTS
1
/INT4
P4
7
/CS
3
P4
6
/CS
2
P4
5
/CS
1
P4
4
/CS
0
P4
3
/HOLD
P4
2
/HOLA
P4
0
/ALE
P3
3
/BHW
P3
2
/BLW
P3
1
/RD
P4
1
/
φ
1
Processor Status Register PS (1
1)
Direct Page Register
DPR0 (16)
Direct Page Register
DPR1 (16)
Direct Page Register
DPR2 (16)
Direct Page Register
DPR3 (16)
Stack Pointer S (16)
Index Register
Y
(16)
Index Register X (16)
Accumulator B (16)
Accumulator A
(16)
Program Counter PC (16)
Program Bank Register PG (8)
Input Buf
fer Register IB (16)
Data Bank Register DT
(8)
Incrementer/Decrementer (24)
Arithmetic Logic
Unit (16)
Program
Address Register P
A
(24)
Incrementer (24)
Timer TB0 (16)
Watchdog Timer
Timer TB2 (16)
Timer TB1 (16)
UART0 (9)
A-D
converter (10)
Low-order
data (8)
Low-order
address (8)
P4
(7)
P3
(2)
P5
(8)
D-A
1
converter (8)
D-A
0
converter (8)
UART1 (9)
Instruction Register (8)
Instruction Queue Buf
fer Q
9
(8)
Instruction Queue Buf
fer Q
8
(8)
Instruction Queue Buf
fer Q
7
(8)
Instruction Queue Buf
fer Q
6
(8)
Instruction Queue Buf
fer Q
5
(8)
Instruction Queue Buf
fer Q
4
(8)
Instruction Queue Buf
fer Q
3
(8)
Instruction Queue Buf
fer Q
2
(8)
Instruction Queue Buf
fer Q
1
(8)
Instruction Queue Buf
fer Q
0
(8)
Data Buf
fer DQ
3
(8)
Data Buf
fer DQ
2
(8)
Data Buf
fer DQ
1
(8)
Data Buf
fer DQ
0
(8)
Data
Address Register DA
(24)
High-order
address(8)/P0
(8)
High-order
Data (8)/P2
(8)
Middie-order
address(8)/P11
(8)
17
16
15
14
13
12
11
10
45
44
43
42
41
40
39
38
53
52
51
50
49
48
47
46
63
62
61
60
59
58
57
56
71
70
69
68
67
66
65
64
79
78
77
76
75
74
73
72
25
24
29
26
23
22
20
19
18
P6
(8)
9
8
7
6
5
4
3
2
P7
(8)
100
99
98
97
96
95
94
1
P8
(8)
Input/Output
port P8
Input/Output
port P7
Input/Output
port P6
Input/Output
port P5
Input/Output
port P4
Data bus/
Input/Output
port P2
(Note 1)
Data bus
Data Bus (Even)
Data Bus (Odd)
Address Bus
Address bus
Address bus/Input/Output
port P0,P11 (Note 2)
Input/
Output
port P3
93
86
85
84
83
82
81
80
31
35
36
Note 1: When the external data bus width = 16 bits, this serves as the data bus; when the external data bus width = 8 bit, this serves as the I/O port.
2: According to the register setting, this can serve as the I/O port.
Clock Generating
Circuit
Clock input
X
IN
Clock output
X
OUT
32
Reset input
RESET
CDSEL
87
37
Vcc
91
55
34
(0V)
Vss
33
(5V)
MD
0
54
(0V)
MD
1
90
(0V)
AVss
88
AVcc
89
Reference
voltage input
V
BEF
92
NMI
30
External data bus
width select input
BYTE
28
Read output
RD
27
Write output
BLW
21
CS0
output
CS
0
Bus
Interface
Unit
(BIU)
DVD P.C.B.
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TEL 13942296513 QQ 376315150 892498299