Yamaha HTR-5063, Руководство по обслуживанию

Страница: 60 / 130

60
RX-V567/HTR-5063
RX-V567/HTR-5063
No.
Function Name
(P.C.B.)
TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of Function
51 EM_D[1] IO – N EMIF data bus [lower 16-bits]
52 EM_D[0] IO – N EMIF data bus [lower 16-bits]
53 CVDD
54 VSS
55 EM_D[15] IO – N EMIF data bus [lower 16-bits]
56 EM_D[14] IO – N EMIF data bus [lower 16-Bits]
57 CVDD
58 EM_D[13] IO – N EMIF data bus [lower 16-Bits]
59 EM_D[12] IO – N EMIF data bus [lower 16-Bits]
60 DVDD
61 EM_D[11] IO – N EMIF data bus [lower 16-Bits]
62 VSS
63 EM_D[10] IO – N EMIF data bus [lower 16-Bits]
64 EM_D[9] IO – N EMIF data bus [lower 16-Bits]
65 CVDD
66 EM_D[8] IO – N EMIF data bus [lower 16-bits]
67 EM_WE_DQM[1] O – N Write enable or byte enable for EM_D [15:8]
68 DVDD
69 VSS
70 EM_CLK O – N SDRAM clock
71 EM_CKE O – N SDRAM clock enable
72 VSS
73 DVDD
74 EM_A[11] O – N EMIF address bus
75 EM_A[9] O – N EMIF address bus
76 EM_A[8] O – N EMIF address bus
77 CVDD
78 VSS
79 EM_A[7] O – N EMIF address bus
80 EM_A[6] O – N EMIF address bus
81 DVDD
82 VSS
83 EM_A[5] O – N EMIF address bus
84 EM_A[4] O – N EMIF address bus
85 CVDD
86 EM_A[3] O – N EMIF address bus
87 VSS
88 EM_A[2] O – N EMIF address bus
89 EM_A[1] O – N EMIF address bus
90 CVDD
91 EM_A[0] O – N EMIF address bus
92 DVDD
93 EM_A[10] O – N EMIF address bus
94 EM_BA[1] O – N SDRAM bank address and asynchronous memory Low-Order address
95 VSS
96 EM_BA[0] O – N SDRAM bank address and asynchronous memory Low-Order address
97 EM_CS[0] O – N SDRAM chip select
98 EM_RAS O – N SDRAM row address strobe
99 VSS
100 EM_CS[2] O – N Asynchronous memory chip select