Yamaha HTR-3072, Руководство по обслуживанию

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Pin No. Function Name (P.C.B.) I/O Detail of Function
76 EMB_D[14] / GP6[14] I/O EMIFB SDRAM data bus
77 CVDD
78 EMB_D[13] / GP6[13] I/O EMIFB SDRAM data bus
79 EMB_D[12] / GP6[12] I/O EMIFB SDRAM data bus
80 EMB_D[11] / GP6[11] I/O EMIFB SDRAM data bus
81 DVDD
82 EMB_D[10] / GP6[10] I/O EMIFB SDRAM data bus
83 EMB_D[9] / GP6[9] I/O EMIFB SDRAM data bus
84 EMB_D[8] / GP6[8] I/O EMIFB SDRAM data bus
85 EMB_WE_DQM[1] / GP5[14] O EMIFB write enable/data mask for EMB_D
86 EMB_CLK O EMIF SDRAM clock
87 DVDD
88 EMB_SDCKE O EMIFB SDRAM clock enable
89 EMB_A[12] / GP3[13] O EMIFB SDRAM row/column address bus
90 DVDD
91 EMB_A[11] / GP7[13] O EMIFB SDRAM row/column address bus
92 EMB_A[9] / GP7[11] O EMIFB SDRAM row/column address bus
93 CVDD
94 EMB_A[8] / GP7[10] O EMIFB SDRAM row/column address bus
95 EMB_A[7] / GP7[9] O EMIFB SDRAM row/column address bus
96 EMB_A[6] / GP7[8] O EMIFB SDRAM row/column address bus
97 EMB_A[5] / GP7[7] O EMIFB SDRAM row/column address bus
98 EMB_A[4] / GP7[6] O EMIFB SDRAM row/column address
99 DVDD
100 EMB_A[3] / GP7[5] O EMIFB SDRAM row/column address
101 EMB_A[2] / GP7[4] O EMIFB SDRAM row/column address
102 EMB_A[1] / GP7[3] O EMIFB SDRAM row/column address
103 EMB_A[0] / GP7[2] O EMIFB SDRAM row/column address
104 CVDD
105 EMB_A[10] / GP7[12] O EMIFB SDRAM row/column address bus
106 EMB_BA[1] / GP7[0] O EMIFB SDRAM bank address
107 EMB_BA[0] / GP7[1] O EMIFB SDRAM bank address
108 EMB_CS[0] O EMIFB SDRAM chip select 0
109 DVDD
110 EMB_RAS O EMIFB SDRAM row address strobe
111 AXR0[0]/AFSR2/GP3[0] I/O McASP0 serial data
I/O McASP2 serial data
112 AXR0[1]/ ACLKX2/GP3[1] I/O McASP0 serial data
I/O McASP2 transmit bit clock
113 AXR0[2]/ AXR2[3]/GP3[2] I/O McASP0 serial data
I/O McASP2 serial data
114 CVDD
115 AXR0[3]/ AXR2[2]/GP3[3] I/O McASP0 serial data
I/O McASP2 serial data
116 AXR0[4]/ AXR2[1]/GP3[4] I/O McASP0 serial data
I/O McASP2 serial data
117 AXR0[5]/ AFSX2/GP3[5] I/O McASP0 serial data
I/O McASP2 transmit frame sync
118 AXR0[6]/ ACLKR2/GP3[6] McASP0 serial data
119 DVDD
120 AXR0[7]/GP3[7] I/O McASP0 serial data
121 AXR0[8]/GP3[8] I/O McASP0 serial data
122 UART1_RXD/AXR0[9]/GP3[9] I UART1 receive data
I/O McASP0 serial data
123 UART1_TXD/AXR0[10]/GP3[10] O UART1 transmit data
I/O McASP0 serial data
124 AXR0[11]/ AXR2[0]/GP3[11] I/O McASP0 serial data
I/O McASP2 serial data
125 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] I/O McASP0 transmit master clock
I/O McASP2 transmit master clock
I USB_REFCLKIN. Optional 48 MHz clock input
126 ACLKX0/ECAP0/APWM0/GP2[12] I/O McASP0 transmit bit clock
I/O Enhanced capture 0 input or auxiliary PWM 0 output
127 AFSX0/GP2[13]/BOOT[10] I/O McASP0 transmit frame sync
I BOOT[10]
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RX-V385/HTR-3072
RX-V385/HTR-3072