A
1
2
3
4
5
6
7
8
9
10
B
C
D
E
F
G
H
I
J
K
L
M
N
79
DIGITAL 3/4
HTR-2064/NS-B20/NS-C20/NS-SWP20
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
IC246
CB241
DIGITAL IN
IC241
:
D70YE101BRFP266
Floating-point digital signal processors
256
256
C67x+ Microprocessor
D1
64
R/W
Data
D2
R/W
Program
Fetch
Memory
Controller
Program/Data
RAM
256K Bytes
JTAG EMU
McASP DMA Bus
Peripheral Configuration Bus
McASP0
16 Serializes
McASP1
6 Serializes
McASP2
2 Serializes
DIT Only
SPI1
SPI0
I2C0
I2C1
RTI
PLL
Program/Data
ROM Page1
256K Bytes
Program/Data
ROM Page2
256K Bytes
Program/Data
ROM Page3
256K Bytes
High-performance
Crossbar Switch
CSP
PMP DMP
Program
Cache
32K Bytes
I/O
I/O
MAX0
MAX1
Events
In
CONTROL
dMAX
EMIF
Peripheral Interrupt and DMA Events
Interrupts
Out
INT
Data
256
256
256
256
32
32
32
32
32
32
32
32
32
32
32
64
32
32
32
32
32
32
32
32
32
32
VDD
A3
A2
A1
A0
A10/AP
A12
A13
CS
RAS
CAS
WE
LDQM
VDD
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VSSQ
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A9
A11
NC
CKE
CLK
UDQM
NC
VSS
VDDQ
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSSQ
VSSQ
VDDQ
DQ15
VSS
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
IC242
: M12L64164A-5TG
1M x 16-bit x 4 banks synchronous DRAM
CLK
CS
RAS
CAS
WE
C
ommand Decoder
C
ontr
ol Logic
Latch Cir
cuit
Input & Output
Buf
fer
R
o
w Decoder
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
CKE
Address
Clock
Generator
Row
Address
Buffer
Column
Address
Buffer
and
and
Refresh
Counter
Refresh
Counter
Mode
Register
Bank B
Bank C
Bank D
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
RY/BY#
WP#/ACC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
AM: MSB address
A0-AM
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
IC243
: MX29LV160DBTI-70G
16M-bit 3V supply flash memory
to DIGITAL 2/4
to DIGITAL 4/4
to DIGITAL 4/4
to DIGITAL 1/4