A
1
2
3
4
5
6
7
8
9
10
B
C
D
E
F
G
H
I
J
K
L
M
N
YSP-900
57
★
All voltages are measured with a 10M
Ω
/V DC electronic volt meter.
★
Components having special characteristics are marked
s
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
POINT
A-3 pin 13 of IC24
DSP 3/3
3.4
3.3
3.2
3.4
0.1
3.4
1.6
0.1
0
0
3.3
3.4
3.4
3.2
3.2
1.5
0
1.6
3.2
3.2
3.2
0
0
3.2
3.1
1.2
0
0
3.2
3.2
3.2
3.2
3.3
0
0
3.2
3.2
0
0
0
0
0
0
3.0
3.2
3.2
3.4
0
0
3.2
3.3
0
0.4
0
0
0
0
0
0
0.4
0
0
0
3.2
3.2
0
3.2
3.4
3.2
0
0
0
3.2
0
3.2
3.4
0
0
0
3.3
0
3.1
0
0
0
3.2
0
3.2
3.3
0.1
0
3.3
3.3
3.3
0
3.3
3.3
3.0
0
0
0
0
0
0
0
3.2
3.3
3.3
3.3
3.3
0
0
3.3
3.2
1.7
1.7
1.7
3.3
2.0
5.0
0
0
1.6
3.2
3.3
4.1
0
0
0
2.1
2.1
0
3.3
1.7
1.7
1.7
3.3
0
0
0
5.0
0
0
0
0
2.4
2.4
3.2
3.3
4.8
0
3.3
3.2
3.1
2.6
3.3
3.2
1.7
1.7
0.7
0
0
0
1.7
1.7
1.7
2.5
0.9
2.5
3.3
3.3
0
2.5
3.3
1.6
0.7
1.5
1.5
1.5
1.5
1.5
1.5
0
0
0
0
0
0
0
0
2.5
1.1
2.5
3.3
1.7
0
2.5
3.3
3.3
0
2.5
3.3
1.5
1.5
1.5
1.5
1.5
0
3.3
3.2
3.1
2.6
3.3
3.2
1.7
1.7
1.7
1.7
2.5
0.7
0
0
0
1.1
2.5
3.3
3.3
0
0
0
2.5
0
1.7
0
0
0
0.9
B-1
2
1
DSP
DAC
SW
EEPROM
MICROPROCESSOR
INTERFACE
EXTERNAL RAM
INTERFACE
CONTROL REGISTER
SDBCK
O
MPLO
AD
/CS
SO
SI
SCK
IOPOR
T
19~0
CASN
RASN
RAMWEN
RAMOEN
SDO0
SDI0
SDI1
SDI2
SDI3
SDI4
SDI5
SDI6
SDI7
SDBCK
SDWCK
XO
XI
CPO
SDI INTERF
A
C
E
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
32 bit DSP Core
PLL
DSP INTERNAL
OPERATING CLOCK
CK (30.72~40.96MHz)
COEFFICIENT
RAM
16 bit
*
1024
word
PROGRAM
RAM
50 bit
*
1024
word
ADDRESS
RAM
17 bit
*
256
word
CONTROL
SIGNALS
RAMD15~0
RAMA17~0
BCK
OP
SD
WCK
O
WCK
O
P
OV
F
END
D
ATA
R
A
M
32 bit
*
1024
word
SDO INTERF
A
C
E
ZER
OF7R-0L
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
IC21
: S-29630AFJA
CMOS serial EEPROM
Memory array
Address
decoder
Data register
Output buffer
Mode decode logic
Clock generator
VCC
GND
DI
SK
CS
DO
IC18, 19
: YSS930-SZ
DSP
BCKIN
LRCIN
DIN
MCLK
DVDD
AVDD
MUTEB
SDIDEM
SCKDSD
LATI2S
MODE
CSBIWL
ZERO
VOUTL
VOUTR
VMID
AGND
DGND
VREFP VREFN
16
15
14
20
19
18
17
5
6
7
1
2
3
4
13
12
11
8
9
10
IC20, 22
: WM8728
24bit, 192kHz stereo DAC
IC24
: M30626FHPFP
Single-chip 16-bit cmos microcomputer
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
Memory
ROM
(1)
RAM
(2)
A/D converter
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits
X
3 channels)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8
8
8
8
Port P6
8
8
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
SB
ISP
USP
INTB
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Multiplier
7
8
8
Po
rt P10
P
or
t P9
Po
rt P8_5
Po
rt P8
Po
rt P7
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Port P5
Port P4
Port P3
Clock synchronous serial I/O
(8 bits
X
2 channels)
PC
FLG
Timer (16-bit)
Three-phase motor
control circuit
8
8
8
2
Port P11
Port P12
Port P14
Port P13
(3)
<VCC2 ports>
(4)
<VCC1 ports>
(4)
<VCC1 por
ts>
(4)
<VCC2 ports>
(4)
<VCC1 ports>
(4)
(3)
(3)
(3)
P
age 59
to INPUT(2)_CB3
E6
P
age 59
to INPUT(3)_CB902
G7
P
age 60
to INPUT(1)_CB507
J6
P
age 58
to AMP_CB702
D2
Содержание Digital Sound Projector YSP-900
Страница 4: ...YSP 900 4 YSP 900 REMOTE CONTROL PANELS T K A B G E L V models J model BOTTOM PANEL J model ...
Страница 48: ...YSP 900 48 2 A B C D E F G H I J 1 3 4 5 7 6 AMP P C B Side B D709 C3 D712 F2 Q701 F2 Q702 G2 Ref No Location ...
Страница 80: ...YSP 900 80 YSP 900 ...
Страница 81: ...YSP 900 81 ...
Страница 82: ...YSP 900 82 YSP 900 ...