Yamaha CinemaDSP digital RX-Z1, Руководство по обслуживанию

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RX-Z1/DSP-AZ1
RX-Z1/DSP-AZ1
IC27 : YSS910-S (DSP P.C.B.)
DSP6 (Digital Audio Processor)
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0
109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89
VDD VSS
XI
XO
VDD5
/SYNCI
/SYNCO
VDD5
CKI
CK
O
CKSEL
VSS
MCKS
/SSYNC
/IC
/TEST
BTYP
/IRQ
TRIG
VDD5
VSS
/CS
/WR
/RD
CA7 CA6 CA5 CA4 CA3 CA2 CA1
VSS VDD
CD15 CD14 CD13 CD12 CD1
1
CD10
CD9 CD8 CD7 CD6 VSS
VDD
VDD5
DB12
DB11
DB10
DB09
DB08
DB07
DB06
DB05
DB04
DB03
DB02
DB01
DB00
VSS
SO7
SO6
SO5
SO4
SO3
SO2
SO1
SO0
VDD5
VSS
SI7
SI6
SI5
SI4
SI3
SI2
SI1
SI0
VSS
/WAIT
CD00
CD01
CD02
CD03
CD04
CD05
VDD5
VDD
VDD VSS D
A15
D
A14
D
A13
D
A12
DA
1
1
D
A10
D
A09
D
A08
VSS D
A07
D
A06
D
A05
D
A04
D
A03
D
A02
D
A01
D
A00
VDD5 VSS TIMO/DBOE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 VDD VSS DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 VSS
NC
VDD5
DA16
DA17
DA18
DA19
DA20
DA21
DA22
DA23
VSS
DA24
DA25
DA26
DA27
DA28
DA29
DA30
DA31
VDD5
VSS
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
VSS
VDD
A10
A11
A12
A13
A14
A15/RAS
A16/CAS
A17/CE
/WE
/OE
VDD5
CPU
INTERFACE
I/O BUS
CONTROL
320 STEP
DEQ
320 STEP
DSP
320CH
INTERPOLATER
EXTERNAL
RAM
INTERFACE
MOD
8 BIT/16CH
FUNCTION
PARALLEL
IN/OUT
SERIAL
OUTPUT
32CH OUTPUT
BUFFER
SERIAL
INPUT
32CH INPUT
BUFFER
CD14~00 CA7~0 BTYP /WR /CS /RD /IRQ TRIG /W
AIT
SI0~7
SO0~7
DB31~00
/DB0E
CLOCK
GENERATOR
XO XI CKI /SYNCO /SYNCI CK
O
CKSEL MCKS /SSYNC /IC /TEST
CTL-BUS
I/O-BUS
DA31~00
A17~00
/WE
/OE
15
32
18
8
8 8
32
Name
XI
XO
/SYNCI
CKI
/SYNCO
CKO
CKSEL
MCKS
/SSYNC
/IC
/TEST
CD14-00
CA0/CD15
CA7-1
BTYP
/CS
/RD
/WR
/IRQ
TRIG
/WAIT
SI7-0
SO7-0
DB31-00
TIMO/DBOE
DA31-00
A17/CE
A16/CAS
A15/RAS
A14-12
A11-00
/WE
/OE
(N.C.)
VDD5
VDD
VSS
I/O
I
O
I
I
O
O
I
I
I
Is
I+
I/O
I/O
I
I
Is+
Is+
Is+
O
I/O
O
I+
O
I+/O
I/O
I+/O
O
O
O
O
O
O
O
_
_
_
_
Function
System master clock input (60MHz or 30MHz)
System master clock output (60MHz or 30MHz)
System synchronous signal input
System clock input (30MHz)
System synchronous signal output
System clock output (30MHz)
System master clock select (0:60MHz, 1: 30MHz)
Master clock input for serial I/O (128 x Fs)
Synchronous signal input for serial I/O
Initial clear
Test mode setting (0: Test, 1: Normal)
Host CPU data bus
Host CPU address bus / data bus
Host CPU address bus
Host CPU data bus width select (0: 8 bit, 1: 16 bit)
Chip select signal input
Read signal input
Write signal input
IRQ output
Transfer trigger signal input/output
WAIT output
Serial data input
Serial data output
Parallel data bus
Timing signal output / parallel data bus output control input
External memory data bus
External memory address (SRAM), /CE (PSRAM)
External memory address (SRAM, PSRAM), /CAS (DRAM)
External memory address (SRAM, PSRAM), /RAS (DRAM)
External memory address (SRAM, PSRAM)
External memory address (SRAM, PSRAM, DRAM)
External memory Write Enable signal
External memory Output Enable signal
+5V
+3.3V
Ground
No connection
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