Yamaha 01x, Руководство по обслуживанию

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25
O1X
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
IRERRN
IRCVN
IRXN
VDD
VSS
ICLK
CYCLEOUT
ICS
CT
ITXN
VDD
VSS
NC
NC
SCANE
TSTI0
TSTI1
TSTI2
TSTI3
VSS
ITREQN
VDD
IEOPN
NC
NC
NC
VSS
IDATA0
IDATA1
NC
NC
IDATA2
VDD
IDATA3
IDATA4
IDATA5
VSS
NC
IDATA6
IDATA7
NC
IDATA8
VDD
IDATA9
IDATA10
IDATA11
VSS
IDATA12
IDATA13
IDATA14
VDD
IDATA15
SEQO
DBC
VSS
LOCKN
PCA
PCB
VDD
TSTI4
TSTI5
TSTI6
TSTI7
NC
TXE
VDD
NC
VSS
VCOCLK
SVCO0
SVCO1
SMCK0
NC
NC
SMCK1
SLV
SEQI
VDD
NC
NC
VSS
ECKI
EWCKI
PAR
PDIR
PDE
BCK128I
BCKI
NC
WCKI
VDD
VSS
SWCK
TSTI8
TSTI9
TSTI10
TSTI11
VSS
NC
WCKOD
WCKO
BCKO
VDD
NC
I
I
I
-
-
I
I
I
I
I
I
I
-
-
I
I
I
I
I
-
OD
-
OD
-
-
-
-
I/O
I/O
-
-
I/O
-
I/O
I/O
I/O
-
-
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
O
O
-
O
O
O
-
I
I
I
I
-
I/O
-
-
-
I
I
I
I
-
-
I
I
I
-
-
-
-
I
I
I
I
I
I
I
-
I
-
-
I/O
I
I
I
I
-
-
O
O
O
-
-
Isochronous packet error flag input (Low active)
Isochronous reception enable input (Low active)
Isochronous reception data enable input (Low active)
+3.3 V
Ground
Isochronous master clock input (24.576MHz)
Isochronous cycle out signal input
Isochronous cycle start signal input
Isochronous cycle timer enable input
Isochronous transmission data enable input (Low active)
+3.3 V
Ground
Input for LSI test (usually connected to ground)
Input for LSI test (usually connected to ground)
Ground
Isochronous transmission request output (Low active)
+3.3 V
Isochronous transmission packet test data signal output (Low active)
Ground
Isochronous data input/output
Isochronous data input/output
+3.3 V
Isochronous data input/output
Ground
Isochronous data input/output
Isochronous data input/output
+3.3 V
Isochronous data input/output
Ground
Isochronous data input/output
+3.3 V
Isochronous data input/output
Loop connection output when 2 to 4 chips are used simultaneously
DBC timing output
Ground
PLL lock flag output (Low active)
Output for PLL external phase comaparator
Output for PLL external phase comaparator
+3.3 V
Input for LSI test (usually connected to ground)
Enable output (for master), input (for slave) for multi-chip transmission
+3.3 V
Ground
PLL external VCO clock input
VCO frequency setting input
VCO frequency setting input
MCKO clock division rate setting input
MCKO clock division rate setting input
0: Master, 1: Slave when 2 to 4 chips are used simultaneously
Loop connection input when 2 to 4 chips are used simultaneously
+3.3 V
Ground
Bit clock inout for receptin from outside (128Fs or 256Fs)
Word clock input for reception from output (Fs)
Selection of serial, parallel input/output, 0: Serial, 1: Parallel
Parallel data direction input, 0: Input, 1: Output
Parallel data enable input
Bit clock input for digital audio input (128Fs)
Bit clock input for digital audio input (32Fs to 128Fs)
Word clock input for digitral audio input (Fs)
+3.3 V
Ground
Word clock output (for master), input (for slave) for multi-chip transmission
Input for LSI test (usually connected to ground)
Ground
Delay output of WCKO (Fs)
Word clock output for digital audio output (Fs)
Bit clock output for digital audio output (64Fs)
+3.3 V
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208 BCK128O
MCKO
VSS
ECKO
EWCKO
VDD
PCLK
VSS
NC
PDIO0
NC
PDIO1
VDD
PDIO2
PDIO3
PDIO4
VSS
PDIO5
PDIO6
PDIO7
NC
VDD
NC
NC
VDD
VSS
NC
VDD
NC
PDIO8
PDIO9
NC
PDIO10
VSS
PDIO11
PDIO12
NC
PDIO13
VDD
PDIO14
NC
PDIO15
PDIO16
VSS
PDIO17
PDIO18
PDIO19
VDD
PDIO20
PDIO21
PDIO22
VSS
PDIO23
PDIO24
PDIO25
VDD
PDIO26
PDIO27
PDIO28
VSS
PDIO29
PDIO30
PDIO31
VDD
HD0
HD1
NC
NC
HD2
VSS
HD3
HD4
HD5
VDD
HD6
NC
NC
HD7
IRQN
VSS
NC
TSTI12
TSTI13
NC
TSTI14
VDD
VSS
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
VDD
VSS
NC
ICN
CSN
WRN
NC
RDN
O
O
-
O
O
-
O
-
-
I/O
-
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
I/O
I/O
-
I/O
-
I/O
I/O
-
I/O
-
I/O
-
I/O
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
I/O
-
-
I/O
-
I/O
I/O
I/O
-
I/O
-
-
I/O
OD
-
-
I
I
-
I
-
-
I
I
I
I
I
I
I
I
I
-
-
-
I
I
I
-
I
Bit clock output for digital audio output (128Fs)
Master clock output for digital audio output (64Fs to 384Fs)
Ground
Bit clock output for reception to outside (128Fs or 256Fs)
Word clock output for reception to outside (Fs)
+3.3 V
Parallel data transfer clock output (128Fs or 256Fs)
Ground
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
+3.3 V
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Ground
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
+3.3 V
+3.3 V
Ground
3.3 V
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
+3.3 V
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
Ground
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
+3.3 V
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
Ground
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
+3.3 V
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
Ground
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
3.3 V
Data input/output
Data input/output
Ground
Data input/output
+3.3 V
Data input/output
Data input/output
Interrupt request output (Low active)
Ground
Input for LSI test (usually connected to ground)
Input for LSI test (usually connected to ground)
+3.3 V
Ground
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
+3.3 V
Ground
Initial clear input (Low active)
Chip select input (Low active)
Write enable input (Low active)
Read enable input (Low active)
YTS440B-F (X3009B00) mLAN-PH2 (mLAN
TM
Packet Handler 2)
MLN2: IC007