Yamaha 01V96, Руководство по обслуживанию

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39
01V96
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CDOUT
/CS
/EMPH
RXP0
RXN0
VA+
AGND
FILT
/RST
RMCK
RERR
RXP1
RXP2
RXP3
O
I
O
I
I
O
O
I/O
O
I
I
I
Data out (SPI)
Control port chip select (SPI)
Pre-emphasis
AES3/SPDIF receiver port
Positive analog power 5V
Analog ground
PLL loop filter
Reset
Input section recovered master clock
Receiver error
Additional AES3/SPDIF receiver port
15
16
17
18
19
20
21
22
23
24
25
26
27
28 RXP4
OSCLK
OLRCK
SDOUT
INT
U
OMCK
DGND
VL+
H//S
RXP5
RXP6
CDIN
CCLK
I
I/O
I/O
O
O
O
I
I
I
I
I
I
Additional AES3/SPDIF receiver port
Serial audio output bit clock
Serial audio output left/right clock
Serial audio output data
Interrupt
User data
System clock
Digital ground
Positive logic power 5V
Hardware/software mode control
Additional AES3/SPDIF receiver port
Serial control data in (SPI)
Control port clock
CS8415A-CS (X2089A00) DIR (Digital Audio Interface Receiver)
MAIN: IC501
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
COREV
DD
/WAIT
DB15
DB14
DB13
DB12
DB11
DB10
DB9
IOV
DD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V
SS
COREV
DD
GPIO0
FPDAT11
FPDAT10
FPDAT9
FPDAT8
V
SS
FPSHIFT
IOV
DD
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
FPLINE
FPFRAME
V
SS
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Power 3.3V
Wait signal
Data bus
Power 3.3V
Data bus
Ground
Power 3.3V
General purpose input/output
Panel data
Ground
Shift clock
Power 3.3V
Panel data
Line pulse
Frame pulse
Ground
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 COREV
DD
DRDY
LCDPWR
TESTEN
CNF4
CNF3
CNF2
CNF1
CNF0
V
SS
CLKI
IOV
DD
AB15
AB14
AB13
AB12
AB11
AB10
AB9
V
SS
COREV
DD
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
BCLK
V
SS
/RESET
/CS
/BS
/RD
/WE0
/WE1
RD//WR
V
SS
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Power 3.3V
TFT/D-TFD display enable
LCD power control
Test enable input
Configure the S1D13704
Ground
Input clock
Power 3.3V
Address bus
Ground
Power 3.3V
Address bus
System bus clock
Ground
Reset
Chip select signal
Bus start signal
Read signal
Write enable signal for the lower data byte
Write enable signal for the upper data byte
Read/write signal
Ground
S1D13704F00A100 (X3498A00) LCDC (LCD Controller)
MAIN: IC019