Xycom Xembedded XPMC-6710, Справочное руководство

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Overview
Document Number: 646710 17
GPIO Configuration
Each GPIO pin can be configured as an input, an input with open-drain capability, or an output.
The GPIOs are connected to the Tsi109 Host Bridge GPIO pins. The GPIO Interface has a set
of output latches, which depending on configuration, either drive the output enables or the
output pins. The Interface also has a set of input buffers that provides the state of the GPIO
pins and can be read at any time.
The GPIO pins can also be used as additional interrupt inputs by mapping the pins to one or
more of the four interrupt output pins. Each pin can be configured to generate an interrupt on
an edge-detected transition (low-to-high or a high-to-low), or a level-detected state. Table 1
below list the location and destination of the GPIOs.
Table 1
GPIOs Signals and Destinations
Signal Destination
GPIO0 J4, Pin 35
GPIO1 J4, Pin 36
GPIO2 J4, Pin 37
GPIO3 J4, Pin 38
GPIO4 J4, Pin 39
GPIO5 J4, Pin 40
GPIO6 J4, Pin 41
GPIO7 J4, Pin 42
GPIO8 R6: Pull up to SW2 Pin 8
GPIO9 R7: To on-board CPLD (not used by default)
GPIO10 SEL/F/B: Select front or rear connection for
the Gigabit Ethernet port). This pin by default
has a pull down. Driving the pin high and
routes the Gigabit to the front. Default = Front
(the open boot drives this pin high)
GPIO11 *MR: Master Reset, pulling this pin low will
reset the board
GPIO12 LED0 (Front Panel) see note
GPIO13 LED1 (Front Panel) see note
GPIO14 LED2 (Front Panel) see note
GPIO15 LED3 (Front Panel) see note
NOTE: *All LED's (LED0 to LED3) are active low.