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Document MT1503P.A
© Xsens Technologies B.V.
Hardware Integration Manual MTi 1-series
3.2.3 SPI
For the SPI interface, PSEL1 can be left floating or pulled-up to VDDIO and PSEL0 pin needs to be
connected to GND, as shown in Figure 4.
Figure 4: Connections (SPI interface)
3.2.4 UART
For the UART full-duplex interface, PSEL1 and PSEL0 pins needs to be connected to GND, as shown
in Figure 5. The UART full-duplex communications mode can be used without hardware flow control. In
this case the CTS line needs to be tied low (GND) to make the MTi 1-series transmit. For UART
half-duplex interface, PSEL1 needs to be connected to GND and PSEL0 pin must be left floating (see
Table 5).
Figure 5: Connections (UART interface full-duplex)
