xcore.ai Explorer v2 Board Manual
GPIO
Port
signal
X0D37
P1N
I2C_SCL
X0D38
P1O
I2C_SDA
X1D11
P1D
I2S_MCLK
X1D01
P1B
I2S_LRCLK
X1D10
P1C
I2S_BCLK
X1D00
P1A
I2S_DAC_DATA
X1D37
P1N
I2S_ADC_DATA
X1D09
P4A3
CODEC_RESET
The I2S signals are on the VDDIOR domain, the I2C signals are on the VDDIOL domain but
are routed through level shifters, enabling the CODEC to use VDDIOR for its I/O voltage.
The master clock, which is provided to both the xcore.ai and the CODEC for synchronisa-
tion, is generated by a PLL that is integrated in the xcore.ai device, see
for
more details.
2.5 QSPI Flash
The xcore.ai explorer board includes 4 Mbytes of external Quad Serial Peripheral Interface
(QSPI) FLASH memory, which is interfaced by the GPIO connections as per the standard
prescribed in the datasheet:
GPIO
Port
QSPI connection
X0D01
P1B
CS_N
X0D04
P4B0
IO0
X0D05
P4B1
IO1
X0D06
P4B2
IO2
X0D07
P4B3
IO3
X0D10
P1C
SPI_CLK
The XTC tools include the xFLASH utility for programming compiled programs into the
flash memory. xcore.ai applications may also access the FLASH memory at run-time by
interfacing through those ports.
2.6 LPDDR memory
The xcore.ai explorer board includes 128 Mbytes of external LPDDR memory. They are
connected as documented in the application note on xcore.ai External LPDDR Memory,
2.7 GPIO headers (J10-J16)
Most of the GPIO are brought out on headers J10-J16 so that external devices can be
connected to the explorer board. The connectors are along the left hand side of the
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